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    Semiconductor devices and methods of fabricating the same
    1.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US09559112B2

    公开(公告)日：2017-01-31

    申请号：US14472952

    申请日：2014-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaegoo Lee ,  Youngwoo Park ,  Jungdal Choi

    IPC: H01L27/115 ,  H01L29/78 ,  H01L29/423 ,  H01L29/792

    CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7827 ,  H01L29/7926

    Abstract: A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

    Abstract translation: 一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。 该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二 牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过 去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。

    Nonvolatile memory device
    3.
    发明授权
    Nonvolatile memory device 有权
    非易失性存储器件

    公开(公告)号：US08923058B2

    公开(公告)日：2014-12-30

    申请号：US13653798

    申请日：2012-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyun Lee ,  Yoocheol Shin ,  Jungdal Choi

    IPC: G11C16/04 ,  G11C5/06 ,  G11C5/02 ,  G11C5/04 ,  G11C11/34

    CPC classification number: G11C11/34 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

    Abstract: A nonvolatile memory device is provided. The device may include a plurality of cell strings that are configured to share a bit line, word lines, and selection lines. Each of the cell strings may include a plurality of memory cells connected in series to each other and a string selection device controlling connections between the memory cells and the bit line, and the string selection device may include a first string selection element with a first threshold voltage and a second string selection element connected in series to the first string selection element and having a second threshold voltage different from the first threshold voltage. At least one of the first and second string selection elements may include a plurality of switching elements connected in series to each other.

    Abstract translation: 提供非易失性存储器件。 该设备可以包括被配置为共享位线，字线和选择线的多个单元串。 每个单元串可以包括彼此串联连接的多个存储器单元和用于控制存储器单元和位线之间的连接的串选择装置，并且串选择装置可以包括具有第一阈值的第一串选择元件 电压和第二串选择元件串联连接到第一串选择元件并且具有不同于第一阈值电压的第二阈值电压。 第一和第二串选择元件中的至少一个可以包括彼此串联连接的多个开关元件。

    ERASING METHOD OF RESISTIVE RANDOM ACCESS MEMORY
    4.
    发明申请
    ERASING METHOD OF RESISTIVE RANDOM ACCESS MEMORY 审中-公开
    电阻随机存取存储器的擦除方法

    公开(公告)号：US20130301340A1

    公开(公告)日：2013-11-14

    申请号：US13796808

    申请日：2013-03-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JINTAEK PARK ,  Youngwoo Park ,  Jungdal Choi

    IPC: G11C13/00

    CPC classification number: G11C13/0097 ,  G11C13/0064 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/78 ,  G11C2213/79

    Abstract: An erase method of a resistive random access memory which includes a plurality of cell strings, each having a plurality of memory cells and a string selection transistor, includes applying a first voltage to bit lines connected with string selection transistors of the plurality of cell strings, applying a turn-on voltage to at least one string selection line selected from string selection lines connected with the string selection transistors, applying a turn-off voltage to unselected string selection lines of the string selection lines, applying a second voltage to at least one word line selected from word lines connected with memory cells of the plurality of cell strings, and floating unselected word lines of the word lines.

    Abstract translation: 一种电阻随机存取存储器的擦除方法，包括多个单元串，每个单元串具有多个存储单元和串选择晶体管，包括将第一电压施加到与多个单元串中的串选择晶体管连接的位线， 对从与串选择晶体管连接的串选择线中选择的至少一个串选择线施加接通电压，向串选择线的未选择的串选择线施加截止电压，将第二电压施加到至少一个 从与多个单元串中的存储单元相连的字线选择的字线和字线的浮动未选字线。

    Vertical resistance memory device and a read method thereof
    5.
    发明授权
    Vertical resistance memory device and a read method thereof 有权
    垂直电阻存储器件及其读取方法

    公开(公告)号：US09036398B2

    公开(公告)日：2015-05-19

    申请号：US13708018

    申请日：2012-12-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

    IPC: G11C11/00 ,  G11C11/21 ,  G11C13/00

    CPC classification number: G11C11/21 ,  G11C8/12 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C16/0408 ,  G11C16/08 ,  G11C2213/71 ,  G11C2213/78

    Abstract: A read method of a vertical resistance memory device including resistance memory cells arranged in a three-dimensional array includes selecting a block from a plurality of blocks, applying a read voltage to a word line selected from word lines of the block, applying a sensing reference voltage to bit lines sharing the plurality of blocks, applying a string selection voltage to a string selection transistor through a string selection line selected from a plurality of string selection lines of the block, wherein the string selection line is connected to a gate of the string selection transistor; and determining a memory state of a memory cell selected from the plurality of resistance memory cells by the word line and the string selection line based on a current flowing through the memory cell, wherein the word line is connected through a corresponding horizontal electrode to the memory cell.

    Abstract translation: 包括以三维阵列布置的电阻存储单元的垂直电阻存储器件的读取方法包括从多个块中选择一个块，向从块的字线选择的字线施加读取电压，施加感测参考 共享多个块的电压对位线，通过从块的多个串选择线中选择的串选择线将字符串选择电压施加到字符串选择晶体管，其中字符串选择线连接到字符串的门 选择晶体管; 并且基于流过所述存储单元的电流，通过所述字线和所述串选择线来确定从所述多个电阻存储单元中选择的存储单元的存储状态，其中所述字线通过相应的水平电极连接到所述存储器 细胞。

    Vertical nonvolatile memory devices and methods of operating same
    6.
    发明授权
    Vertical nonvolatile memory devices and methods of operating same 有权
    垂直非易失性存储器件及其操作方法

    公开(公告)号：US08953382B2

    公开(公告)日：2015-02-10

    申请号：US14164586

    申请日：2014-01-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaesung Sim ,  Jungdal Choi

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/14

    CPC classification number: G11C16/344 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/3418

    Abstract: Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).

    Abstract translation: 集成电路存储器件包括多个垂直堆叠的非易失性存储器单元串，其中各个垂直布置的沟道区域在其中电耦合到下面的衬底。 提供了一种控制电路，其被配置为在擦除时间间隔期间以从第一电压电平斜坡到较高的第二电压电平的擦除电压驱动垂直沟道区。 擦除电压的上升促进了垂直堆叠的非易失性存储器单元的时间有效的擦除，从而降低了对无意编程接地和串选择晶体管（GST，SST）的敏感性。

    VERTICAL RESISTANCE MEMORY DEVICE AND A PROGRAM METHOD THEREOF
    7.
    发明申请
    VERTICAL RESISTANCE MEMORY DEVICE AND A PROGRAM METHOD THEREOF 审中-公开
    垂直电阻存储器件及其程序方法

    公开(公告)号：US20130223128A1

    公开(公告)日：2013-08-29

    申请号：US13708042

    申请日：2012-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jintaek Park ,  Jungdal Choi

    IPC: G11C7/00 ,  G11C11/21

    CPC classification number: G11C7/00 ,  G11C5/06 ,  G11C11/16 ,  G11C11/21 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79

    Abstract: A method of programming a vertical resistance memory device including a plurality of resistance memory cells arranged in a plurality of blocks includes a step of selecting a block from the plurality of blocks, a step of applying a set voltage to a word line selected from word lines, wherein the selected word line is connected through a corresponding horizontal electrode to a resistance memory cell to be programmed, a step of applying a set-inhibition voltage to unselected word lines of the word lines, a step of applying a bit voltage to a bit line selected from bit lines, wherein the selected bit line is electrically connected to the resistance memory cell via a string selection transistor selected from string selection transistors; and a step of applying a bit-inhibition voltage to unselected bit lines of the bit lines.

    Abstract translation: 一种编程包括布置在多个块中的多个电阻存储单元的垂直电阻存储器件的方法包括从多个块中选择块的步骤，将设定电压施加到从字线选择的字线 ，其中所选择的字线通过相应的水平电极连接到要被编程的电阻存储单元，将设置禁止电压施加到字线的未选字线的步骤，将位电压施加到位 从位线选择的线，其中所选择的位线经由串选择晶体管选择的串选择晶体管电连接到电阻存储单元; 以及将位抑制电压施加到位线的未选位线的步骤。

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