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公开(公告)号：US07920370B2
公开(公告)日：2011-04-05
申请号：US11987835
申请日：2007-12-05
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
摘要： A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.
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公开(公告)号：US07733628B2
公开(公告)日：2010-06-08
申请号：US12005300
申请日：2007-12-27
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
摘要： A multilayer chip capacitor including: a capacitor body having a plurality of dielectric layers deposited therein and having a parallelepiped shape; at least three pairs of first and second external electrodes formed on two longer sides, the first and second external electrodes in each of the pairs having different polarities and opposing each other, and the first and second external electrodes on each of the longer sides arranged alternately with each other; and a plurality of first and second internal electrodes arranged alternately to interpose each of the dielectric layers, the first and second internal electrodes connected to the first and second external electrodes by leads, respectively, wherein the capacitor body has a length that is 2.5 times greater than a width thereof.
摘要翻译： 一种多层片状电容器，包括：具有沉积在其中并具有平行六面体形状的多个电介质层的电容器主体; 形成在两个长边上的至少三对第一和第二外部电极，每对中的第一和第二外部电极具有不同的极性并且彼此相对，并且每个长边上的第一和第二外部电极交替布置 彼此; 并且交替地布置多个第一和第二内部电极以分别插入每个电介质层，第一和第二内部电极分别通过引线连接到第一和第二外部电极，其中电容器主体具有2.5倍的长度 比其宽度。
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公开(公告)号：US20090034154A1
公开(公告)日：2009-02-05
申请号：US12010018
申请日：2008-01-18
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005
摘要： A multilayer chip capacitor includes: a capacitor body; internal electrodes disposed in the capacitor body, each internal electrode having one or more lead; and external electrodes disposed on first and second side surfaces of the capacitor body to be electrically connected to the internal electrodes through the leads. The average number of leads in each internal electrode is smaller than half (½) of the total number of external electrodes. The leads of the internal electrodes having opposite polarities and adjacent in the lamination direction are disposed to be adjacent to each other as seen from the lamination direction. All the internal electrodes having the same polarity are electrically connected to each other in the capacitor.
摘要翻译： 多层片状电容器包括：电容器本体; 设置在电容器本体中的内部电极，每个内部电极具有一个或多个引线; 以及设置在电容器主体的第一和第二侧面上的外部电极，以通过引线与内部电极电连接。 每个内部电极的引线平均数小于外部电极总数的一半（1/2）。 具有相反极性并且在层叠方向上相邻的内部电极的引线设置成从层叠方向看彼此相邻。 具有相同极性的所有内部电极在电容器中彼此电连接。
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14.发明授权Multilayer chip capacitor, motherboard apparatus having the same, and power distribution network 有权多层片式电容器，具有相同的主板设备和配电网络公开(公告)号：US08159813B2
公开(公告)日：2012-04-17
申请号：US12270330
申请日：2008-11-13
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
CPC分类号： H01G4/385 , H01G4/005 , H01G4/30 , H01L2224/16227 , H01L2924/15311 , H01L2924/19105
摘要： There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged in a laminated direction; and first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively, wherein the first capacitor unit includes first and second inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing a corresponding one of dielectric layers, the second capacitor unit includes third and fourth inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing another corresponding one of the dielectric layers, the first and second capacitor units are electrically insulated from each other, and the first capacitor unit operates in a first frequency range and the second capacitor unit operates in a second frequency range lower than the first frequency range.
摘要翻译： 提供了一种多层片状电容器，包括：电容器体，包括沿层叠方向布置的第一和第二电容器单元; 以及分别形成在电容器主体的侧面上的第一至第四外部电极，其中，所述第一电容器单元包括交替布置在所述电容器体中的第一和第二内部电极，所述第一和第二内部电极彼此相对，同时插入相应的一个电介质层， 所述第二电容器单元包括具有不同极性的第三和第四内部电极，所述第三和第四内部电极交替地布置在所述电容器体中，以相对于彼此相对，同时插入另一个对应的一个所述介电层，所述第一和第二电容器单元彼此电绝缘， 单元在第一频率范围内操作，并且第二电容器单元在低于第一频率范围的第二频率范围内操作。
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公开(公告)号：US07679882B2
公开(公告)日：2010-03-16
申请号：US12238688
申请日：2008-09-26
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
摘要： There is provided a multilayer chip capacitor capable of tuning capacitance, including: a capacitor body where a plurality of dielectric layers are laminated; a plurality of pairs of first and second internal electrodes arranged alternately, while interposing a corresponding one of the dielectric layers; and a plurality of pairs of first and second external electrodes connected to the first and second internal electrodes, wherein the first and second internal electrodes include a plurality of groups each including at least one pair of the first and second internal electrodes, and the first and second internal electrodes of each of the groups are connected to different pairs of the first and second external electrodes, respectively, wherein a corresponding one of the pairs of the first and second external electrodes is selectively connected to power lines so that the multilayer chip capacitor has at least two different capacitances.
摘要翻译： 提供一种能够调谐电容的多层片状电容器，包括：电容器体，层叠多个电介质层; 多个成对的第一和第二内部电极交替布置，同时插入相应的一个电介质层; 以及连接到所述第一和第二内部电极的多对第一和第二外部电极，其中所述第一和第二内部电极包括多个组，每个组包括至少一对所述第一和第二内部电极，以及所述第一和第二内部电极 每个组的第二内部电极分别连接到第一和第二外部电极的不同对，其中第一和第二外部电极对中的相应一个选择性地连接到电力线，使得多层片状电容器具有 至少两个不同的电容。
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公开(公告)号：US07675733B2
公开(公告)日：2010-03-09
申请号：US12237837
申请日：2008-09-25
申请人： Byoung Hwa Lee , Sung Kwon Wi , Sang Soo Park , Min Cheol Park , Dong Seok Park , Hae Suk Chung
发明人： Byoung Hwa Lee , Sung Kwon Wi , Sang Soo Park , Min Cheol Park , Dong Seok Park , Hae Suk Chung
IPC分类号： H01G4/228
摘要： There is provided a multilayer capacitor including an inner connecting conductor of at least one polarity; a plurality of first and second outer electrodes formed on a surface of the body, wherein the inner connecting conductor is connected to a corresponding one of the outer electrodes having identical polarity, a corresponding one of the inner electrodes having identical polarity to the inner connecting conductor includes a plurality of groups each including at least one of the inner electrodes, wherein the inner electrodes of the respective groups are connected to the outer electrodes having identical polarity that are different from one another for each of the groups and electrically connected to the inner connecting conductor through the connected outer electrode.
摘要翻译： 提供一种包括至少一个极性的内连接导体的多层电容器; 形成在所述主体的表面上的多个第一和第二外部电极，其中所述内部连接导体连接到具有相同极性的对应的一个外部电极，相应的一个所述内部电极具有与所述内部连接导体 包括多个组，每个组包括至少一个内部电极，其中各组的内部电极连接到具有与每个组相互不同的极性相同的外部电极，并且电连接到内部连接 导体通过连接的外部电极。
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公开(公告)号：US20090279228A1
公开(公告)日：2009-11-12
申请号：US12267112
申请日：2008-11-07
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/30
摘要： A multilayer chip capacitor includes a capacitor body provided by a stack of a plurality of dielectric layers, a plurality of internal electrodes disposed in the capacitor body such that the internal electrodes of opposite polarities are alternately disposed to face each other with the dielectric layer interposed between each facing set of the internal electrodes, and a plurality of external electrodes disposed on an outer face of the capacitor body and electrically connected with the internal electrode. Each of the plurality of internal electrodes includes a main electrode part, and at least one lead extending from the main electrode part to a side face of the capacitor body and connected to a corresponding one of the external electrodes. The lead extends to the corresponding external electrode to be inclined with respect to the main electrode part thereof.
摘要翻译： 多层片状电容器包括：由多个电介质层的堆叠体构成的电容器主体，设置在电容器主体中的多个内部电极，使得相互极性的内部电极交替地配置成彼此面对，其中介电层介于 每个面对的内部电极组，以及多个外部电极，设置在电容器主体的外表面上并与内部电极电连接。 多个内部电极中的每一个包括主电极部分和从电极主体的主电极部分延伸到侧面的至少一个引线，并连接到对应的一个外部电极。 引线延伸到对应的外部电极，以相对于其主电极部分倾斜。
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公开(公告)号：US07599166B2
公开(公告)日：2009-10-06
申请号：US11598672
申请日：2006-11-14
申请人： Byoung Hwa Lee , Hae Suk Chung , Dong Seok Park , Min Cheol Park , Sang Soo Park , Sung Kwon Wi
发明人： Byoung Hwa Lee , Hae Suk Chung , Dong Seok Park , Min Cheol Park , Sang Soo Park , Sung Kwon Wi
摘要： A multilayer chip capacitor includes a capacitor body having dielectric layers, and internal electrode layers separated from each other in the capacitor body by the dielectric layers. Each internal electrode layer has one or two leads and includes at least one coplanar electrode plate. External electrodes are electrically connected to the internal electrode layers via the leads. The internal electrode layers constitute a plurality of blocks stacked repeatedly. Each block includes a plurality of the internal electrode layers stacked successively. The leads extending to a face of the capacitor body are arranged in a zigzag shape along a stacking direction. The leads of vertically adjacent ones of the electrode plates having opposite polarities are arranged to be horizontally adjacent to each other.
摘要翻译： 多层片状电容器包括具有电介质层的电容器主体，以及通过电介质层在电容器主体中彼此分离的内部电极层。 每个内部电极层具有一个或两个引线并且包括至少一个共面电极板。 外部电极通过引线电连接到内部电极层。 内部电极层构成反复堆叠的多个块。 每个块包括依次层叠的多个内部电极层。 延伸到电容器主体的表面的引线沿堆叠方向布置成Z字形。 具有相反极性的垂直相邻电极板的引线被布置成水平相邻。
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19.发明授权公开(公告)号：US07595973B1
公开(公告)日：2009-09-29
申请号：US12262909
申请日：2008-10-31
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/005 , H01G4/30 , H05K1/0231 , H05K1/113 , H05K2201/10636 , Y02P70/611
摘要： There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units disposed in a laminated direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively; and at least one connecting conductor line connecting the first and third outer electrodes having identical polarity to each other and the second and fourth outer electrodes having identical polarity to each other, wherein the first capacitor body includes first and second inner electrodes, the second capacitor unit includes a plurality of third and fourth inner electrodes, the first to fourth outer electrodes are connected to the first to fourth inner electrodes, respectively, and an equivalent series resistance (R1) of the first capacitor unit and a combined equivalent series resistance (R2′) of the second capacitor and the connecting conductor line satisfy the Equation 0.7(R1)≦R2′≦1.3(R1).
摘要翻译： 提供了一种多层片状电容器，包括：电容器主体，包括沿层叠方向设置的第一和第二电容器单元; 分别形成在电容器主体的侧表面上的第一至第四外部电极; 以及连接第一和第三外部电极的至少一个连接导线，彼此具有相同的极性，第二和第四外部电极彼此具有相同的极性，其中第一电容器主体包括第一和第二内部电极，第二电容器单元 包括多个第三和第四内部电极，第一至第四外部电极分别连接到第一至第四内部电极，并且第一电容器单元的等效串联电阻（R1）和组合的等效串联电阻（R2' ）和连接导线满足公式0.7（R1）<= R2'<= 1.3（R1）。
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公开(公告)号：US20090086406A1
公开(公告)日：2009-04-02
申请号：US12238796
申请日：2008-09-26
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/228
摘要： There is provided a multilayer capacitor including: a capacitor body where a plurality of dielectric layers are laminated, the capacitor body including first and second surfaces opposing each other in a laminated direction, wherein the first surface provides a mounting surface; a plurality of first and second inner electrodes; an inner connecting conductor; and a plurality of first and second outer electrodes formed on an outer surface of the body, wherein a corresponding one of the outer electrodes having identical polarity to the inner connecting conductor includes at least one outer terminal formed on the first surface of the body to connect to the inner connecting conductor, and at least one outer connecting conductor formed on the second surface of the body to connect a corresponding one of the inner electrodes of identical polarity to the inner connecting conductor.
摘要翻译： 提供了一种层叠电容器，其包括：层叠多个电介质层的电容器体，所述电容器主体包括在层叠方向上彼此相对的第一和第二表面，其中所述第一表面提供安装表面; 多个第一和第二内部电极; 内连接导体; 以及形成在所述主体的外表面上的多个第一外部电极和第二外部电极，其中与所述内部连接导体具有相同极性的相应的外部电极包括形成在所述主体的所述第一表面上的至少一个外部端子，以连接 内部连接导体和形成在主体的第二表面上的至少一个外部连接导体，以将相当极性的相应的一个内部电极与内部连接导体相连接。
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