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公开(公告)号:US20240334598A1
公开(公告)日:2024-10-03
申请号:US18614865
申请日:2024-03-25
Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Inventor: Yuki KOBAYASHI , Tomoo YAMASAKI
CPC classification number: H05K1/09 , H05K1/0373 , H05K1/113 , H05K3/108 , H05K2201/0209 , H05K2201/0338 , H05K2203/072 , H05K2203/0723
Abstract: A wiring substrate includes a first wiring layer, an insulation layer covering a side surface of the first wiring layer and exposing part of the first wiring layer, and a second wiring layer formed on the first wiring layer exposed from the insulation layer. The insulation layer includes a resin and a filler. The insulation layer includes an upper surface having a structure in which the filler is exposed from the resin. The second wiring layer includes a first metal film, covering the upper surface of the insulation layer and the wiring layer exposed from the insulation layer, and a metal layer, formed above the first metal film. The first metal film is formed from a CuNiTi alloy and has a Ni content rate of 5 wt % or greater and 30 wt % or less and a Ti content rate of 5 wt % or greater and 15 wt % or less.
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公开(公告)号:US12107082B2
公开(公告)日:2024-10-01
申请号:US18368424
申请日:2023-09-14
Applicant: Intel Corporation
Inventor: Russell K. Mortensen , Robert M. Nickerson , Nicholas R. Watts
IPC: H01L21/00 , H01L21/44 , H01L21/48 , H01L21/50 , H01L21/56 , H01L21/60 , H01L23/00 , H01L23/02 , H01L23/28 , H01L23/31 , H01L23/48 , H01L23/488 , H01L23/498 , H01L23/52 , H01L23/538 , H01L23/552 , H01L25/00 , H01L25/065 , H01L25/10 , H01L25/11 , H01L25/18 , H05K1/02 , H05K1/11 , H05K3/40
CPC classification number: H01L25/18 , H01L21/4846 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/03 , H01L24/09 , H01L24/11 , H01L24/17 , H01L24/43 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/89 , H01L25/0657 , H01L25/105 , H01L25/50 , H05K1/113 , H05K3/4038 , H01L24/16 , H01L24/32 , H01L24/48 , H01L2224/0401 , H01L2224/0557 , H01L2224/08238 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/48245 , H01L2224/48472 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/143 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1511 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/381 , Y10T29/49124 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00012 , H01L2924/15311 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00012 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00 , H01L2224/73265 , H01L2224/32145 , H01L2224/48227 , H01L2924/00012 , H01L2924/00014 , H01L2224/05552 , H01L2224/48091 , H01L2924/00014 , H01L2924/00014 , H01L2224/45099 , H01L2924/00014 , H01L2224/45015 , H01L2924/207 , H01L2224/48472 , H01L2224/48227 , H01L2924/00
Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
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公开(公告)号:US20240284604A1
公开(公告)日:2024-08-22
申请号:US18503462
申请日:2023-11-07
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor: Myungju Gi
CPC classification number: H05K3/4608 , H05K1/036 , H05K1/113 , H05K1/115 , H05K3/0014 , H05K2203/0323
Abstract: Disclosed is a circuit board including: an insulation layer for burying at least one wire layer and at least one via layer and having a first side and a second side facing each other, and a first wire layer partly protruding over the first side of the insulation layer and partly buried in the insulation layer, wherein the insulation layer has a concave cavity dented from the first side, and part of the via layer is exposed from the insulation layer through a bottom side of the cavity.
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公开(公告)号:US12048095B2
公开(公告)日:2024-07-23
申请号:US17430708
申请日:2020-02-10
Applicant: LG INNOTEK CO., LTD.
Inventor: Min Young Hwang , Moo Seong Kim , Byeong Kyun Choi
CPC classification number: H05K1/113 , H05K1/0207 , H05K1/0296 , H05K2201/096
Abstract: A circuit board according to one embodiment comprises a first insulation layer, a circuit pattern on the first insulation layer, and a second insulation layer on the circuit pattern, wherein a heat transfer member is arranged inside the first insulation layer and/or the second insulation layer, and the heat transfer member is arranged while coming in contact with a side surface of the insulation layer.
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公开(公告)号:US12016119B2
公开(公告)日:2024-06-18
申请号:US17542706
申请日:2021-12-06
Applicant: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. , Avary Holding (Shenzhen) Co., Limited.
Inventor: Cheng-Jia Li , Mei Yang
CPC classification number: H05K1/09 , H05K1/113 , H05K1/115 , H05K3/02 , H05K3/4608 , H05K3/4673 , H05K2201/0352 , H05K2201/09381 , H05K2201/09518 , H05K2201/0959 , Y10T29/49126
Abstract: A method for manufacturing such multilayer printed circuit board includes providing a metal laminated structure including a first type metal layer and a second type metal layer, pressing a patterned dry film layer and a protective film layer on two surfaces of the metal laminated structure, the dry film layer exposing the second type metal layer; etching the second type metal layer to form a first conductive circuit layer; etching a first type metal layer to form a second conductive circuit layer, the first conductive circuit layer and the second conductive circuit layer defining an inner circuit laminated structure; removing the dry film layer; and forming a first adding-layer circuit base board and a second adding-layer circuit base board on two surfaces of the inner laminated structure.
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公开(公告)号:US20240188215A1
公开(公告)日:2024-06-06
申请号:US18314099
申请日:2023-05-08
Applicant: TONG HSING ELECTRONIC INDUSTRIES, LTD.
Inventor: LI-CHUN HUNG
CPC classification number: H05K1/113 , H01L24/48 , H01L2224/48228 , H01L2224/48453 , H01L2224/48464 , H01L2924/37001 , H01L2924/386 , H05K2201/032 , H05K2201/09745
Abstract: A circuit substrate having an improved bonding structure includes a substrate core layer, an upper protective layer, and at least one bond finger portion. The substrate core layer has a top surface and a bottom surface. The upper protective layer is formed on the top surface of the substrate core layer. The upper protective layer has at least one channel. The at least one bond finger portion is formed on the top surface of the substrate core layer, and is disposed in the at least one channel. A plurality of protrusions are formed on an upper surface of the at least one bond finger portion, so as to increase a bonding area with a bonding wire.
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公开(公告)号:US11978730B2
公开(公告)日:2024-05-07
申请号:US17587664
申请日:2022-01-28
Applicant: Intel Corporation
Inventor: Russell K. Mortensen , Robert M. Nickerson , Nicholas R. Watts
IPC: H01L21/00 , H01L21/44 , H01L21/48 , H01L21/50 , H01L21/56 , H01L21/58 , H01L21/60 , H01L23/00 , H01L23/02 , H01L23/13 , H01L23/28 , H01L23/31 , H01L23/34 , H01L23/44 , H01L23/48 , H01L23/488 , H01L23/498 , H01L23/50 , H01L23/52 , H01L23/538 , H01L23/552 , H01L23/66 , H01L25/00 , H01L25/065 , H01L25/10 , H01L25/11 , H01L25/16 , H01L25/18 , H05K1/11 , H05K3/40
CPC classification number: H01L25/18 , H01L21/4846 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/03 , H01L24/09 , H01L24/11 , H01L24/17 , H01L24/43 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/89 , H01L25/0657 , H01L25/105 , H01L25/50 , H05K1/113 , H05K3/4038 , H01L24/16 , H01L24/32 , H01L24/48 , H01L2224/0401 , H01L2224/0557 , H01L2224/08238 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/48245 , H01L2224/48472 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/143 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1511 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/381 , Y10T29/49124 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00012 , H01L2924/15311 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00012 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00 , H01L2224/73265 , H01L2224/32145 , H01L2224/48227 , H01L2924/00012 , H01L2924/00014 , H01L2224/05552 , H01L2224/48091 , H01L2924/00014 , H01L2924/00014 , H01L2224/45099 , H01L2924/00014 , H01L2224/45015 , H01L2924/207 , H01L2224/48472 , H01L2224/48227 , H01L2924/00
Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
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公开(公告)号:US20240136267A1
公开(公告)日:2024-04-25
申请号:US18277654
申请日:2022-02-17
Applicant: LG INNOTEK CO., LTD.
Inventor: Hyun Sun LEE , Dae Sung MOON , Dong Hun JOUNG
IPC: H01L23/498 , H01L23/00 , H05K1/11
CPC classification number: H01L23/49827 , H01L24/32 , H05K1/113 , H05K1/115 , H01L2224/32235 , H01L2924/1432
Abstract: A semiconductor package according to an embodiment includes a first insulating layer; and a first through electrode part passing through the first insulating layer and having a shape elongated in a first direction; wherein the first through electrode part includes a plurality of first through electrodes spaced apart from each other in a second direction perpendicular to the first direction and a thickness direction; wherein at least one of the plurality of first through electrodes includes a first sub through electrode and a second sub through electrode spaced apart from each other in the first direction; and wherein at least one of the first sub through electrode and the second sub through electrode has a width in the first direction greater than a width in the second direction.
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9.
公开(公告)号:US20240131339A1
公开(公告)日:2024-04-25
申请号:US18547999
申请日:2022-03-10
Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Inventor: Shadi A. Dayeh , Youngbin Tchoe , Andrew M. Bourhis
CPC classification number: A61N1/36125 , A61N1/0531 , H05K1/113 , H05K1/181 , H05K3/32 , H05K2201/041 , H05K2201/10325 , H05K2201/10378 , H05K2203/0384 , H05K2203/1305
Abstract: A flexible electrode array with hundreds or thousands channels for clinical use includes an array of at least hundreds of electrodes on a flexible biocompatible polymer substrate. Perfusion through holes are provided through the substrate. Individual elongate leads connect to each of the electrodes, the elongate lead connections being supported by the flexible biocompatible polymer substrate and extending away from the array. Flexible biocompatible polymer insulates the individual elongate lead connections and supporting the array. An interposer with individual channel connections is conductively bonded to the individual elongate lead connections. Sterile bag packaging encloses a portion of the interposer, where the outer side of the package including the array and individual elongate lead is sterile while the inner side of the packaging is non-sterile. The portion interposer inside the package is configured to connect to a circuit board within the packaging.
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公开(公告)号:US20240114619A1
公开(公告)日:2024-04-04
申请号:US18073592
申请日:2022-12-02
Applicant: InnoLux Corporation
Inventor: Cheng-Chi WANG , Chin-Ming HUANG , Chien-Feng LI , Chia-Lin YANG
CPC classification number: H05K1/113 , H05K3/4038 , H05K3/4673 , H05K2201/0266
Abstract: An electronic device including an electronic unit and a redistribution layer is disclosed. The electronic unit has connection pads. The redistribution layer is electrically connected to the electronic unit and includes a first insulating layer, a first metal layer and a second insulating layer. The first insulating layer is disposed on the electronic unit and has first openings disposed corresponding to the connection pads. The first metal layer is disposed on the first insulating layer and electrically connected to the electronic unit through the connection pads. The second insulating layer is disposed on the first metal layer. The first insulating layer includes first filler particles, and the second insulating layer includes second filler particles. The first filler particles have a first maximum particle size, the second filler particles have a second maximum particle size, and the second maximum particle size is greater than the first maximum particle size.
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