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26 条记录 (耗时 0.019 秒)

    3:2 Bit compressor circuit and method
    11.
    发明申请
    3:2 Bit compressor circuit and method 审中-公开
    3：2位压缩机电路及方法

    公开(公告)号：US20070233760A1

    公开(公告)日：2007-10-04

    申请号：US11392070

    申请日：2006-03-29

    申请人： Sanu Mathew ,  Ram Krishnamurthy ,  Zheng Guo

    发明人： Sanu Mathew ,  Ram Krishnamurthy ,  Zheng Guo

    IPC分类号： G06F7/00 ,  G06F15/00

    CPC分类号： G06F7/501 ,  G06F7/5016

    摘要： A circuit to convert three input bits (A, B and C) to a redundant format may include a first block with at least one transmission gate, and a second block with at least one static mirror. The first block may receive the three bits and output a sum bit, and the second block may receive the three bits and output a carry bit.

    摘要翻译： 将三个输入位（A，B和C）转换为冗余格式的电路可以包括具有至少一个传输门的第一块和具有至少一个静态镜的第二块。 第一块可以接收三位并输出和位，第二块可以接收三位并输出进位位。

    Reconfigurable SIMD vector processing system
    13.
    发明授权
    Reconfigurable SIMD vector processing system 有权
    可重构SIMD矢量处理系统

    公开(公告)号：US07519646B2

    公开(公告)日：2009-04-14

    申请号：US11586810

    申请日：2006-10-26

    申请人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F2207/3828

    摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

    摘要翻译： 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

    Boosted multiplexer transmission gate
    16.
    发明授权
    Boosted multiplexer transmission gate 有权
    升压复用器传输门

    公开(公告)号：US06404237B1

    公开(公告)日：2002-06-11

    申请号：US09752063

    申请日：2000-12-29

    申请人： Sanu Mathew ,  Ram Krishnamurthy ,  Krishnamurthy Soumyanath

    发明人： Sanu Mathew ,  Ram Krishnamurthy ,  Krishnamurthy Soumyanath

    IPC分类号： H03K19094

    CPC分类号： H03K17/6872 ,  H03K17/063 ,  H03K17/693

    摘要： An apparatus and method for boosting a transmission gate by charging a pair of capacitors and using the coupling effect of that pair of capacitors to overdrive the gate inputs of NMOS and PMOS transistors of a transmission gate to turn on the transistors more strongly and speed the passage of data signals.

    摘要翻译： 一种用于通过对一对电容器充电并且使用该对电容器的耦合效应来过载驱动传输门极的NMOS和PMOS晶体管的栅极输入以更强烈地导通晶体管并加速通路的装置和方法 的数据信号。

    Graphics lighting engine including log and anti-log units
    17.
    发明授权
    Graphics lighting engine including log and anti-log units 有权

    公开(公告)号：US09852540B2

    公开(公告)日：2017-12-26

    申请号：US13976920

    申请日：2011-12-31

    申请人： Farhana Sheikh ,  Sanu Mathew ,  Ram Krishnamurthy

    发明人： Farhana Sheikh ,  Sanu Mathew ,  Ram Krishnamurthy

    IPC分类号： G06T15/50

    CPC分类号： G06T15/50 ,  G06T15/506

    摘要： Disclosed is an apparatus and method for generating a lighting value based on a number of lighting factors. A lighting accelerator first converts an ambient portion, a diffuse light portion, and a specular light portion of the lighting factors into the log domain. Then, data combination units operate on the lighting factors after they have been converted. Then, the lighting factors are converted back from the log domain using anti-log processing. Converting the lighting factors into the log domain is accomplished by using a series of linear equations using coefficients that are all based on powers of two, and are therefore easily calculable. Further, while in the log domain, the specular light portion of the lighting factor is operated on by a special purpose multiplier that uses a truncated partial product tree, saving area and power with only a negligible amount of error.

    GRAPHICS LIGHTING ENGINE INCLUDING LOG AND ANTI-LOG UNITS
    18.
    发明申请
    GRAPHICS LIGHTING ENGINE INCLUDING LOG AND ANTI-LOG UNITS 有权
    图形照明发动机，包括日志和防盗单元

    公开(公告)号：US20140028677A1

    公开(公告)日：2014-01-30

    申请号：US13976920

    申请日：2011-12-31

    申请人： Farhana Sheikh ,  Sanu Mathew ,  Ram Krishnamurthy

    发明人： Farhana Sheikh ,  Sanu Mathew ,  Ram Krishnamurthy

    IPC分类号： G06T15/50

    CPC分类号： G06T15/50 ,  G06T15/506

    摘要： Disclosed is an apparatus and method for generating a lighting value based on a number of lighting factors. A lighting accelerator first converts an ambient portion, a diffuse light portion, and a specular light portion of the lighting factors into the log domain. Then, data combination units operate on the lighting factors after they have been converted. Then, the lighting factors are converted back from the log domain using anti-log processing. Converting the lighting factors into the log domain is accomplished by using a series of linear equations using coefficients that are all based on powers of two, and are therefore easily calculable. Further, while in the log domain, the specular light portion of the lighting factor is operated on by a special purpose multiplier that uses a truncated partial product tree, saving area and power with only a negligible amount of error.

    摘要翻译： 公开了一种基于多个照明因素产生照明值的装置和方法。 照明加速器首先将照明因素的环境部分，漫射光部分和镜面光部分转换成对数域。 然后，数据组合单元在转换后对照明因素进行操作。 然后，使用反日志处理将照明因素从日志域转换回来。 将照明因子转换为对数域是通过使用一系列线性方程来实现的，这些方程全部基于二次幂，因此易于计算。 此外，在对数域中，照明因子的镜面光部分由专用乘法器操作，该专用乘法器使用截断的部分乘积树，仅以可忽略的误差量来节省面积和功率。

    Multiplier product generation based on encoded data from addressable location
    19.
    发明授权
    Multiplier product generation based on encoded data from addressable location 有权
    基于可寻址位置的编码数据的乘数乘积生成

    公开(公告)号：US08078662B2

    公开(公告)日：2011-12-13

    申请号：US11540346

    申请日：2006-09-29

    申请人： Sanu Mathew ,  Vishak Venkatraman ,  Steven K. Hsu ,  Ram Krishnamurthy

    发明人： Sanu Mathew ,  Vishak Venkatraman ,  Steven K. Hsu ,  Ram Krishnamurthy

    IPC分类号： G06F7/533

    CPC分类号： G11C7/1006 ,  G06F7/533 ,  G06F7/5332 ,  G06F7/5334 ,  G06F7/74

    摘要： For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds to the first number and that is encoded for partial product reduction, and second circuitry to generate a product based at least in part on the encoded data and on data corresponding to a second number. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，装置包括至少部分地基于对应于第一号码的地址从可寻址位置输出编码数据的第一电路，其中编码数据至少部分地基于对应于第一号码的数据 并且其被编码用于部分产品减少，以及第二电路，用于至少部分地基于编码数据和对应于第二数量的数据来生成产品。 还公开了其他实施例。

    Modular multiplication acceleration circuit and method for data encryption/decryption
    20.
    发明授权
    Modular multiplication acceleration circuit and method for data encryption/decryption 失效
    模块化乘法加速电路和数据加密/解密方法

    公开(公告)号：US07693926B2

    公开(公告)日：2010-04-06

    申请号：US11393392

    申请日：2006-03-30

    申请人： Sanu Mathew ,  Ram Krishnamurthy ,  Zheng Guo

    发明人： Sanu Mathew ,  Ram Krishnamurthy ,  Zheng Guo

    IPC分类号： G06F7/38

    CPC分类号： G06F7/728 ,  G06F7/722

    摘要： A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-significant bit of product Z is 1, addition of a least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1, multiplication of the least-significant bit of X and bits 2w-1:w of Y to generate bits 2w-1:w of product Z, and addition of bits 2w-1:w of modulus M to bits 2w-1:w of product Z if the least-significant bit of product Z is 1. Multiplying the least-significant bit of X and bits 2w-1:w of Y may occur at least partially contemporaneously with multiplying the least-significant bit of X and the least-significant w bits of Y, determining if the least-significant bit of product Z is 1, and adding the least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1.

    摘要翻译： 处理乘法器X和被乘数Y的系统可以包括X的最低有效位和Y的最低有效位W的乘法以产生乘积Z的最低有效w位。系统还可以包括确定是否 如果产品Z的最低有效位为1，乘积Z的最低有效位为1，则将乘积Z的最低有效位加上最低有效W位的模M， 的X和位2w-1：w，以产生乘积Z的位2w-1：w，并将模数M的位2w-1：w加到乘积Z的位2w-1：w，如果最不重要 乘积Z为1.乘以X的最低有效位和Y的位2w-1：w可以至少部分同时与X的最低有效位和Y的最低有效位相乘，从而确定 如果乘积Z的最低有效位为1，并将模数M的最低有效位W加到最小值 如果产品Z的最低有效位为1，则不能产生Z位。