Abstract:
A first terminal unit is connected to a line switch via a set of data lines. A second terminal unit is connected to the first terminal unit via a set of data lines. A third terminal unit is connected to the second terminal unit via a set of data lines. Therefore, the terminals are sequentially connected in series. Cells transmitted to the terminals are multiplexed by each terminal and sequentially transmitted upstream, to the third terminal unit, the second terminal unit, and the first terminal unit together with a token. Since the first terminal unit receives a first identification signal from a switch and a second identification signal from downstream, the first terminal unit recognizes that it is the highest order terminal unit, and sends a cell to the switch after separating the cell from a token which is to be returned downstream. Since the second terminal unit does not receive the first identification signal and receives only the second identification signal, it recognizes that it is an intermediate terminal unit, and sends back downstream a token returned from upstream. Since the third terminal unit does not receive the identification signals, it recognizes that it is the lowest order terminal unit, and sends upstream a cell transmitted via a low data rate line according to a token returned from upstream.
Abstract:
A cell having an attribute of a point-to-multipoint connection is distributed to each of a number of subscribers using a point-to-multipoint connection distributing switch to be provided in parallel with a point-to-point connection, concentrating and distributing switch. Therefore, a hardware configuration can be simply established. Besides, both a point-to-point connection, and a point-to-multipoint connection can be made only by switching a cell to each switching unit, and a software configuration can thus be simplified.
Abstract:
A congestion-monitor control apparatus monitors a congestion condition of each output highway in an asynchronous transfer mode switching system transferring cells to output highways by using a cell-storage buffer. The apparatus includes a monitor circuit monitoring the number of cells stored in the cell-storage buffer for each output highway at a plurality of timings during a given monitor time interval. The apparatus further includes a first determination circuit comparing the number of times when the number of cells from the monitor circuit is equal to or more than a first threshold value during the given monitor time interval with a second threshold value and determining whether the congestion has occurred in a corresponding output highway based on a comparison result.
Abstract:
A test cell generating section periodically generates a pass determining test cell at preset timing, multiplexes them with user cells from a user line interface, and transmits the result of multiplexing to an ATM exchange. When no user cell is supplied from the user line interface, the test cell generating section transmits only the pass determining test cell to the ATM exchange. A cell determining section determines whether a cell supplied from the ATM exchange is a user cell or test cell, identifies/determines the pass based on information of the test cell and outputs only the user cell to the user line side when the supplied cell is the test cell.
Abstract:
A self-routing exchange which includes switch modules connected in multiple stages. A synchronous transfer mode (STM) circuit switch module, which is capable of changing over a connection relationship between incoming highways and outgoing highways, is provided between the multistage-connected switch modules and self-routing switch modules. Asynchronous transfer mode (ATM) switch modules are provided as switch modules in preceding and succeeding stages of the circuit switching module. In dependence upon the number m of self-routing switch modules, a controller sets, by means of software, the connection relationship between the incoming and outgoing highways in each of space switches incorporated within the circuit switching module. As a result, the total mn-number of incoming highways from the self-routing switch modules are connected to respective ones of mn-number of outgoing highways set by the controller. In a case where self-routing switch modules are added on later to expand the system, the controller changes the connection relationship between the incoming and outgoing highways in each space switch within the circuit switching module, using software.
Abstract:
A broadband ISDN remote multiplexer, which is constructed by separating a subscriber line interfacing section from an ATM exchange and installing the same at a remote location connected via a high-speed transmission line, comprises: a first interface unit for carrying out conversion between a transmitted signal of UNI format, carrying a destination number in its GFC field and transmitted over a transmission medium interconnecting the ATM exchange and the broadband ISDN remote multiplexer, and a first path-control signal that directs a connection within the remote multiplexer in accordance with the destination number; a plurality of subscriber line interface units for terminating respectively the plurality of broadband ISDN subscriber lines; and a multiplexing/demultiplexing unit for making a connection between the first interface unit and each of the subscriber line interface units in accordance with the first path-control signal.
Abstract:
In a control system for switching between a first system and a second system of a duplicated selecting structure in an ATM exchange, one of the first and second systems operates as an active system, and the other operates as a standby system. A generator unit writes specific bits into ATM cells received via an input transmission line. The specific bits respectively written into ATM cells to be transferred via the active system indicate a first state, and those respectively written into the ATM cells to be transferred via the standby system indicate a second state. A first table stores the specific bits respectively assigned to VPI/VCI pairs related to the ATM cells transferred via the first system. A second table stores the specific bits respectively assigned to VPI/VCI pairs related to the ATM cells transferred via the second system. A selecting unit compares the specific bits written into the ATM cells with the specific bits stored in the first and second tables by using the VPI/VCI pairs of the ATM cells, and outputs only ATM cells respectively having specific bits respectively indicating the first state to an output transmission line.
Abstract:
Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.
Abstract:
A plurality of address creators are provided corresponding to a plurality of memories of ALU modules. The address creators create addresses for reading or writing data from the memories each time a connection configuration is switched. In creating addresses in the memories, the address creators enable operations to be set by using various types of parameters and set values by mounting special-purpose hardware for memory ports, so that addresses can be created at high-speed.
Abstract:
A switching apparatus that is used for high-speed large-capacity routing and a communication apparatus and communication system that are used for an efficient recursive multicast. A matrix switch performs self-routing on a packet on the basis of a tag including output route information set in the packet. Selectors are located so as to correspond to N output ports P#1 through P#N of the matrix switch and perform N-to-one selection control. Setting registers hold selection information used by the selectors to select a signal.