公开(公告)号：US20130107610A1

公开(公告)日：2013-05-02

申请号：US13282299

申请日：2011-10-26

Applicant: Randy W. Mann ,  Scott D. Luning

Inventor： Randy W. Mann ,  Scott D. Luning

IPC: G11C11/34 ,  H01L21/8238 ,  G11C11/00

CPC classification number: H01L27/0207 ,  G11C11/412 ,  H01L27/1104 ,  Y10S257/903

Abstract: A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.

Abstract translation: 提供了一种静态随机存取存储单元，其包括形成在基板上的第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管驻留在掩埋氧化物层下方的第一区域上，并且具有第一掺杂水平和施加的偏压，为下拉晶体管提供第一电压阈值。 一对通道晶体管耦合第一和第二反相器的单元节点，并且每一个形成在掩埋氧化物层下方的第二区域上，并且具有第二掺杂水平，并且施加的偏置为通路晶体管提供第二电压阈值。 第一电压阈值与提供下拉晶体管和通道晶体管之间的电压阈值控制的第二电压阈值不同。

公开(公告)号：US20130107608A1

公开(公告)日：2013-05-02

申请号：US13282261

申请日：2011-10-26

Applicant: Randy W. Mann ,  Scott D. Luning

Inventor： Randy W. Mann ,  Scott D. Luning

IPC: G11C11/00 ,  H01L27/12

CPC classification number: H01L27/1108 ,  G11C11/412 ,  G11C11/419 ,  H01L27/1203

Abstract: A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a first doping level forming first backgates for the pull-down transistors. A pair of passgate transistors respectively couples to the cell nodes of the first and second inverters and each are formed over second regions below the buried oxide layer with the second regions having a second doping level forming second backgates for the passgate transistors. Active bias circuitry applies potentials to the first and second backgates during read, standby and write operations of the static random access memory cell.

Abstract translation: 提供了在衬底上的掩埋氧化物层上的硅层中形成的静态随机存取存储器单元，并且包括第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管形成在掩埋氧化物层下方的第一区域上，其中第一区域具有形成用于下拉晶体管的第一衬底的第一掺杂级。 一对通道晶体管分别耦合到第一和第二反相器的单元节点，并且每一个均形成在掩埋氧化物层下方的第二区域上，其中第二区域具有形成用于通路晶体管的第二衬底的第二掺杂水平。 主动偏置电路在静态随机存取存储器单元的读取，备用和写入操作期间将电位施加到第一和第二后挡板。

公开(公告)号：US07087509B1

公开(公告)日：2006-08-08

申请号：US09676197

申请日：2000-09-28

Applicant: William R. Roche ,  David Donggang Wu ,  Massud Aminpur ,  Scott D. Luning

Inventor： William R. Roche ,  David Donggang Wu ,  Massud Aminpur ,  Scott D. Luning

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/28035 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4916

Abstract: The present invention is directed to a semiconductor device having a gate electrode includes of a plurality of sidewalls, each having a recess formed therein. The present invention is also directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of dopant material in a layer of polysilicon and etching the layer of polysilicon to define a gate electrode having a plurality of sidewalls, each of which have a recess formed therein.

Abstract translation: 本发明涉及一种半导体器件，其具有包括多个侧壁的栅电极，每个侧壁均形成有凹部。 本发明还涉及一种形成半导体器件的方法。 在一个说明性实施例中，该方法包括在多晶硅层中形成掺杂剂材料层并蚀刻多晶硅层以限定具有多个侧壁的栅电极，每个侧壁在其中形成有凹陷。

公开(公告)号：US06617219B1

公开(公告)日：2003-09-09

申请号：US09784628

申请日：2001-02-15

Applicant: Michael P. Duane ,  David D. Wu ,  Massud Aminpur ,  Scott D. Luning

Inventor： Michael P. Duane ,  David D. Wu ,  Massud Aminpur ,  Scott D. Luning

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.

Abstract translation: 提供了一种方法，所述方法包括在衬底的表面上形成栅极电介质，在栅极电介质上方形成导电栅极结构，所述导电栅极结构具有边缘区域，并且形成与所述栅极电介质邻近的源极/漏极延伸（SDE） 导电栅结构。 该方法还包括在导电栅极结构的边缘区域下方的衬底中形成掺杂剂贫化SDE区域。

公开(公告)号：US5614765A

公开(公告)日：1997-03-25

申请号：US478319

申请日：1995-06-07

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1036 ,  H01L2924/0002

Abstract: An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.

Abstract translation: 用于集成电路和用于半导体器件的衬底载体的绝缘分隔的导线和连接通孔的互连级别，使用双镶嵌仅具有一个掩模图案以形成导电线和通孔。 导电线的掩模图案包含​​在绝缘材料中要形成通孔开口的横向扩大区域。 在产生具有横向扩大区域的导电线路开口之后，开口用适形材料填充，其保护材料的蚀刻选择性基本上小于绝缘材料对用于蚀刻绝缘材料的附魔的蚀刻选择性，并且其蚀刻选择性基本上大于 绝缘材料到其附魔。 保形材料被各向异性地蚀刻以在扩大区域中形成侧壁并且移除侧壁之间的材料，而留下留在导电线开口部分中的材料。 侧壁用作通过开口蚀刻的自对准掩模。 保形材料是导电材料，其在形成通孔开口之后留在适当位置或者被去除的绝缘材料。 在前者中，部分填充的导电线路开口与另外的导电材料一起填充，该通孔是相同或不同的导电材料。 在后者中，导电线路开口和通孔用相同的导电材料填充。

公开(公告)号：US09029956B2

公开(公告)日：2015-05-12

申请号：US13282299

申请日：2011-10-26

Applicant: Randy W. Mann ,  Scott D. Luning

Inventor： Randy W. Mann ,  Scott D. Luning

IPC: H01L27/11 ,  G11C11/00 ,  H01L27/02 ,  G11C11/412

CPC classification number: H01L27/0207 ,  G11C11/412 ,  H01L27/1104 ,  Y10S257/903

Abstract: A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.

Abstract translation: 提供了一种静态随机存取存储单元，其包括形成在基板上的第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管驻留在掩埋氧化物层下方的第一区域上，并且具有第一掺杂水平和施加的偏压，为下拉晶体管提供第一电压阈值。 一对通道晶体管耦合第一和第二反相器的单元节点，并且每一个形成在掩埋氧化物层下方的第二区域上，并且具有第二掺杂水平，并且施加的偏置为通路晶体管提供第二电压阈值。 第一电压阈值与提供下拉晶体管和通道晶体管之间的电压阈值控制的第二电压阈值不同。

公开(公告)号：US20080122002A1

公开(公告)日：2008-05-29

申请号：US11532753

申请日：2006-09-18

Applicant: Gen Pei ,  Scott D. Luning ,  Johannes van Meer

Inventor： Gen Pei ,  Scott D. Luning ,  Johannes van Meer

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/7843

Abstract: A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.

Abstract translation: 提供了一种应力增强CMOS电路及其制造方法。 一种制造方法包括以下步骤：在沟道宽度方向上形成与NMOS晶体管相邻的NMOS晶体管和PMOS晶体管，PMOS晶体管和NMOS晶体管由隔离区隔开。 压缩应力衬垫沉积在晶体管和隔离区上，并被蚀刻以从NMOS晶体管和隔离区的一部分去除压应力衬垫。 拉伸应力衬垫沉积在晶体管，隔离区域和压缩应力衬垫上，并被蚀刻以去除覆盖压缩应力衬垫的一部分的拉伸应力衬垫的一部分，并且留下覆盖NMOS晶体管的拉伸应力衬垫 ，隔离区域和压缩应力衬垫的一部分。

公开(公告)号：US07241700B1

公开(公告)日：2007-07-10

申请号：US10969769

申请日：2004-10-20

Applicant: William George En ,  Eric N. Paton ,  Scott D. Luning

Inventor： William George En ,  Eric N. Paton ,  Scott D. Luning

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/0206 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30608 ,  H01L21/823864 ,  H01L29/66636

Abstract: A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region.

Abstract translation: 栅极结构形成在衬底上。 衬底的源极/漏极区域暴露于包含氢氧化铵，过氧化氢和去离子水的溶液中，以蚀刻源极/漏极区域的最上半个半导体端口。

公开(公告)号：US06589847B1

公开(公告)日：2003-07-08

申请号：US09631557

申请日：2000-08-03

Applicant: Daniel Kadosh ,  Scott D. Luning ,  Derick J. Wristers

Inventor： Daniel Kadosh ,  Scott D. Luning ,  Derick J. Wristers

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/6656

Abstract: The present invention is directed to a method of forming halo implant regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, the substrate being doped with a first type of dopant material, and forming halo implant regions in the substrate adjacent the gate electrode by performing at least the following steps: performing a first angled implant process using a dopant material that is of a type opposite to the first type of dopant material and performing a second angled implant using a dopant material that is of the same type as the first type of dopant material. The method concludes with performing at least one additional implantation process to further form source/drain regions for the device.

Abstract translation: 本发明涉及一种在半导体器件中形成卤素注入区的方法。 在一个说明性实施例中，该方法包括在半导体衬底之上形成栅电极，该衬底被掺杂有第一种类型的掺杂剂材料，以及通过至少执行以下步骤在邻近栅极的衬底中形成卤素注入区域：执行 使用与第一类型的掺杂剂材料相反的类型的掺杂剂材料并使用与第一类型的掺杂剂材料具有相同类型的掺杂剂材料来执行第二成角度的注入的第一成角度注入工艺。 该方法的结论是执行至少一个额外的注入工艺以进一步形成器件的源极/漏极区域。

公开(公告)号：US06569606B1

公开(公告)日：2003-05-27

申请号：US09626666

申请日：2000-07-27

Applicant: David Donggang Wu ,  William R. Roche ,  Massud Aminpur ,  Scott D. Luning ,  Karen L. E. Turnqest

Inventor： David Donggang Wu ,  William R. Roche ,  Massud Aminpur ,  Scott D. Luning ,  Karen L. E. Turnqest

IPC: G03C500

CPC classification number: H01L29/66492 ,  G03F7/2002 ,  H01L21/0274 ,  H01L21/26586

Abstract: The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a structure above a semiconducting substrate, forming a layer of photoresist above the structure and the substrate, and positioning the substrate in an exposure tool that has a light source and a focal plane. The method further comprises positioning the surface of the layer of photoresist in an exposure plane that is different from the focal plane of the exposure tool, exposing the photoresist to the light source of the exposure tool while the surface of the photoresist is in the exposure plane, and developing the layer of photoresist to define an opening in the layer of photoresist around the structure on the substrate.

Abstract translation: 本发明涉及一种在半导体器件中形成晕轮植入物的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成结构，在结构和衬底之上形成光致抗蚀剂层，并将衬底定位在具有光源和焦平面的曝光工具中。 该方法还包括将光致抗蚀剂层的表面定位在与曝光工具的焦平面不同的曝光平面中，将光致抗蚀剂暴露于曝光工具的光源，同时光致抗蚀剂的表面处于曝光平面 并且显影所述光致抗蚀剂层以在所述衬底上的所述结构周围的光致抗蚀剂层中限定开口。