公开(公告)号：US07582493B2

公开(公告)日：2009-09-01

申请号：US11538872

申请日：2006-10-05

申请人： Akif Sultan ,  James F. Buller ,  David Donggang Wu

发明人： Akif Sultan ,  James F. Buller ,  David Donggang Wu

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L22/14

摘要： A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.

摘要翻译： 测试结构包括第一和第二多个晶体管。 第一多个晶体管包括第一长度的栅电极。 第二多个晶体管包括与第一长度不同的第二长度的栅电极。 第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。 使用该测试结构的方法包括测量第一和第二多个晶体管的性能度量。 将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较，以识别与第一多个晶体管相关联的随机长度变化分量。

公开(公告)号：US20100214008A1

公开(公告)日：2010-08-26

申请号：US12392645

申请日：2009-02-25

申请人： Ruigang LI ,  David Donggang WU ,  James F. BULLER ,  Jingrong ZHOU

发明人： Ruigang LI ,  David Donggang WU ,  James F. BULLER ,  Jingrong ZHOU

IPC分类号： H01H37/76 ,  H01L29/00

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01H9/50 ,  H01H35/24 ,  H01H77/101 ,  H01L27/11206

摘要： A method of programming a transistor-based fuse structure is provided. The fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.

摘要翻译： 提供了一种编程基于晶体管的熔丝结构的方法。 熔丝结构在具有半导体衬底的半导体器件，形成在半导体衬底上的晶体管器件和形成在半导体衬底上的基于晶体管的熔丝结构的半导体器件中实现。 基于晶体管的熔丝结构包括多个基于晶体管的熔丝，并且该方法开始于从多个基于晶体管的熔丝中选择待编程的第一目标熔丝，以在低电阻/高电流状态下工作 所述第一靶保险丝在所述第一栅极和所述半导体衬底之间具有第一源极，第一栅极，第一漏极和第一栅极绝缘体层。 该方法将第一组编程电压施加到第一源极，第一栅极和第一漏极，以引起第一栅极绝缘体层的击穿，使得电流可以通过第一栅极绝缘体层从第一源极流到第一栅极 ，并且通过第一栅极绝缘体层从第一栅极到第一漏极。

公开(公告)号：US20080085570A1

公开(公告)日：2008-04-10

申请号：US11538872

申请日：2006-10-05

申请人： Akif Sultan ,  James F. Buller ,  David Donggang Wu

发明人： Akif Sultan ,  James F. Buller ,  David Donggang Wu

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L22/14

摘要： A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.

摘要翻译： 测试结构包括第一和第二多个晶体管。 第一多个晶体管包括第一长度的栅电极。 第二多个晶体管包括与第一长度不同的第二长度的栅电极。 第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。 使用测试结构的方法包括测量第一和第二多个晶体管的性能度量。 将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较，以识别与第一多个晶体管相关联的随机长度变化分量。

公开(公告)号：US06569606B1

公开(公告)日：2003-05-27

申请号：US09626666

申请日：2000-07-27

申请人： David Donggang Wu ,  William R. Roche ,  Massud Aminpur ,  Scott D. Luning ,  Karen L. E. Turnqest

发明人： David Donggang Wu ,  William R. Roche ,  Massud Aminpur ,  Scott D. Luning ,  Karen L. E. Turnqest

IPC分类号： G03C500

CPC分类号： H01L29/66492 ,  G03F7/2002 ,  H01L21/0274 ,  H01L21/26586

摘要： The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a structure above a semiconducting substrate, forming a layer of photoresist above the structure and the substrate, and positioning the substrate in an exposure tool that has a light source and a focal plane. The method further comprises positioning the surface of the layer of photoresist in an exposure plane that is different from the focal plane of the exposure tool, exposing the photoresist to the light source of the exposure tool while the surface of the photoresist is in the exposure plane, and developing the layer of photoresist to define an opening in the layer of photoresist around the structure on the substrate.

摘要翻译： 本发明涉及一种在半导体器件中形成晕轮植入物的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成结构，在结构和衬底之上形成光致抗蚀剂层，并将衬底定位在具有光源和焦平面的曝光工具中。 该方法还包括将光致抗蚀剂层的表面定位在与曝光工具的焦平面不同的曝光平面中，将光致抗蚀剂暴露于曝光工具的光源，同时光致抗蚀剂的表面处于曝光平面 并且显影所述光致抗蚀剂层以在所述衬底上的所述结构周围的光致抗蚀剂层中限定开口。

公开(公告)号：US06368926B1

公开(公告)日：2002-04-09

申请号：US09523632

申请日：2000-03-13

申请人： David Donggang Wu

发明人： David Donggang Wu

IPC分类号： H01L21336

CPC分类号： H01L29/66636 ,  H01L21/26513 ,  H01L21/28035 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： The present invention is directed to a method of forming source/drain regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate stack above a semiconducting substrate, forming a recess in said substrate proximate said gate stack, and performing an implantation process to implant dopant atoms into the bottom surface of the recess. The method further comprises forming a layer of epitaxial silicon in the recess, performing a second ion implantation process to form a doped region in at least the epitaxial silicon in the recess, and performing an anneal process to activate the implanted dopant atoms.

摘要翻译： 本发明涉及一种在半导体器件中形成源/漏区的方法。 在一个说明性实施例中，该方法包括在半导体衬底之上形成栅极堆叠，在所述衬底附近形成凹槽，邻近所述栅极堆叠，以及执行注入工艺以将掺杂剂原子注入凹槽的底表面。 该方法还包括在凹陷中形成外延硅层，执行第二离子注入工艺，以在至少凹陷中的外延硅中形成掺杂区，并执行退火工艺以激活注入的掺杂剂原子。

公开(公告)号：US08050077B2

公开(公告)日：2011-11-01

申请号：US12392645

申请日：2009-02-25

申请人： Ruigang Li ,  David Donggang Wu ,  James F. Buller ,  Jingrong Zhou

发明人： Ruigang Li ,  David Donggang Wu ,  James F. Buller ,  Jingrong Zhou

IPC分类号： G11C17/18 ,  G11C17/16 ,  G11C17/14 ,  G11C17/08 ,  G11C17/00

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01H9/50 ,  H01H35/24 ,  H01H77/101 ,  H01L27/11206

摘要： A transistor-based fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.

摘要翻译： 在具有半导体衬底的半导体器件，形成在半导体衬底上的晶体管器件和形成在半导体衬底上的基于晶体管的熔丝结构的半导体器件中实现基于晶体管的熔丝结构。 基于晶体管的熔丝结构包括多个基于晶体管的熔丝，并且该方法开始于从多个基于晶体管的熔丝中选择待编程的第一目标熔丝，以在低电阻/高电流状态下工作 所述第一靶保险丝在所述第一栅极和所述半导体衬底之间具有第一源极，第一栅极，第一漏极和第一栅极绝缘体层。 该方法将第一组编程电压施加到第一源极，第一栅极和第一漏极，以引起第一栅极绝缘体层的击穿，使得电流可以通过第一栅极绝缘体层从第一源极流到第一栅极 ，并且通过第一栅极绝缘体层从第一栅极到第一漏极。

公开(公告)号：US20090090969A1

公开(公告)日：2009-04-09

申请号：US11867743

申请日：2007-10-05

申请人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

发明人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

摘要翻译： 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。

公开(公告)号：US07087509B1

公开(公告)日：2006-08-08

申请号：US09676197

申请日：2000-09-28

申请人： William R. Roche ,  David Donggang Wu ,  Massud Aminpur ,  Scott D. Luning

发明人： William R. Roche ,  David Donggang Wu ,  Massud Aminpur ,  Scott D. Luning

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28035 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4916

摘要： The present invention is directed to a semiconductor device having a gate electrode includes of a plurality of sidewalls, each having a recess formed therein. The present invention is also directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of dopant material in a layer of polysilicon and etching the layer of polysilicon to define a gate electrode having a plurality of sidewalls, each of which have a recess formed therein.

摘要翻译： 本发明涉及一种半导体器件，其具有包括多个侧壁的栅电极，每个侧壁均形成有凹部。 本发明还涉及一种形成半导体器件的方法。 在一个说明性实施例中，该方法包括在多晶硅层中形成掺杂剂材料层并蚀刻多晶硅层以限定具有多个侧壁的栅电极，每个侧壁在其中形成有凹陷。

公开(公告)号：US08687417B2

公开(公告)日：2014-04-01

申请号：US11867743

申请日：2007-10-05

申请人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Akif Sultan ,  Fred Hause ,  Donna Michael

发明人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Akif Sultan ,  Fred Hause

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/02 ,  G11C16/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

摘要翻译： 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。

公开(公告)号：US06872583B1

公开(公告)日：2005-03-29

申请号：US09503838

申请日：2000-02-15

申请人： David Donggang Wu

发明人： David Donggang Wu

IPC分类号： G11C29/00 ,  G11C29/24 ,  H01L23/544 ,  H01L21/66

CPC分类号： H01L22/34 ,  G11C29/006 ,  G11C29/24 ,  G11C2029/5002

摘要： Semiconductor chip design and analysis is enhanced by using a dummy structure for analyzing a test structure in a test chip. According to an example embodiment of the present invention, a dummy structure is formed having structure that is about identical to that of test structure in a test chip. The parasitic capacitance of the dummy structure is determined and used to analyze the test structure. In this manner, the parasitic capacitance associated with the test structure can be accounted for, enhancing the ability to design, test, and debug semiconductor chips.

摘要翻译： 通过使用用于分析测试芯片中的测试结构的虚拟结构来增强半导体芯片设计和分析。 根据本发明的示例性实施例，形成具有与测试芯片中的测试结构大致相同结构的虚拟结构。 确定虚拟结构的寄生电容并用于分析测试结构。 以这种方式，可以考虑与测试结构相关联的寄生电容，增强设计，测试和调试半导体芯片的能力。