公开(公告)号：US08569116B2

公开(公告)日：2013-10-29

申请号：US13171228

申请日：2011-06-28

申请人： Randy W. Mann ,  Kingsuk Maitra ,  Anurag Mittal

发明人： Randy W. Mann ,  Kingsuk Maitra ,  Anurag Mittal

IPC分类号： H01L21/82 ,  H01L21/479 ,  H01L21/44

CPC分类号： H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

摘要翻译： 提供了制造具有鳍式保险丝的集成电路的方法，以及所得到的具有鳍式保险丝的集成电路。 在该方法中，由半导体材料层产生翅片并具有第一端和第二端。 该方法提供了在翅片上从其第一端到其第二端形成导电路径。 导电路径电连接到编程设备，该编程设备能够选择性地将编程电流引导通过导电路径，从而导致导电路径中的结构变化，以增加穿过导电路径的电阻。

公开(公告)号：US07696034B2

公开(公告)日：2010-04-13

申请号：US12128077

申请日：2008-05-28

申请人： Peter J. Geiss ,  Marwan H. Khater ,  Qizhi Liu ,  Randy W. Mann ,  Robert J. Purtell ,  Beth Ann Rainey ,  Jae-Sung Rieh ,  Andreas D. Stricker

发明人： Peter J. Geiss ,  Marwan H. Khater ,  Qizhi Liu ,  Randy W. Mann ,  Robert J. Purtell ,  Beth Ann Rainey ,  Jae-Sung Rieh ,  Andreas D. Stricker

IPC分类号： H01L21/8238

CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

公开(公告)号：US06967351B2

公开(公告)日：2005-11-22

申请号：US10011351

申请日：2001-12-04

申请人： David M. Fried ,  Randy W. Mann ,  K. Paul Muller ,  Edward J. Nowak

发明人： David M. Fried ,  Randy W. Mann ,  K. Paul Muller ,  Edward J. Nowak

IPC分类号： H01L21/8244 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04

CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/785 ,  Y10S257/903

摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.

摘要翻译： 本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。 本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。 如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。 这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。 在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。 用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。 如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作。

公开(公告)号：US06881672B2

公开(公告)日：2005-04-19

申请号：US10723700

申请日：2003-11-26

申请人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

发明人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

IPC分类号： H01L21/8238 ,  H01L21/44

CPC分类号： H01L21/823871 ,  H01L21/823842

摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has silicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.

摘要翻译： 本文公开了选择性硅化半导体结构及其制造方法。 半导体结构在多晶硅线路上存在硅化物，N +扩散区域或N +有源区域与多晶硅线路的N + / P +结处的P +扩散区域或有源区域之间存在硅化物，而N +有源区域和P +活性区域上不存在硅化物 区。 这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。 在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

公开(公告)号：US06815751B2

公开(公告)日：2004-11-09

申请号：US10064301

申请日：2002-07-01

申请人： Jeffrey S. Brown ,  Randy W. Mann

发明人： Jeffrey S. Brown ,  Randy W. Mann

IPC分类号： H01L218234

CPC分类号： H01L27/10861 ,  H01L27/0207 ,  H01L27/1203

摘要： Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.

公开(公告)号：US06778449B2

公开(公告)日：2004-08-17

申请号：US10064302

申请日：2002-07-01

申请人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Randy W. Mann ,  Jeffrey H. Oppold

发明人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Randy W. Mann ,  Jeffrey H. Oppold

IPC分类号： G11C700

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C2029/5006

摘要： A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.

摘要翻译： 用于具有通过导线连接在一起的单元阵列的测试结构的方法和结构。 导线将电池连接在一起，就像它们是单个电池一样。 导线可以包括通用字线; 一个普通的位线 公共位线补码线，公共N阱电压线，公共内部地线，公共内部电压线和/或公共接地线。

公开(公告)号：US06335272B1

公开(公告)日：2002-01-01

申请号：US09637935

申请日：2000-08-14

申请人： Archibald Allen ,  Jerome B. Lasky ,  Randy W. Mann ,  Jed H. Rankin ,  Francis R. White

发明人： Archibald Allen ,  Jerome B. Lasky ,  Randy W. Mann ,  Jed H. Rankin ,  Francis R. White

IPC分类号： H01L214763

CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L21/28568

摘要： A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

摘要翻译： 提供了一种用于其制造的埋地对接接触和方法，其包括具有第一导电类型的掺杂剂并且具有浅沟槽隔离的衬底。 第二导电类型的掺杂剂位于所述衬底中的开口的底部。 在衬底中的掺杂剂和位于开口的侧壁上的低扩散性掺杂剂之间提供欧姆接触。 接触是金属硅化物，金属和/或金属合金。

公开(公告)号：US5510295A

公开(公告)日：1996-04-23

申请号：US145921

申请日：1993-10-29

申请人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Francois M. d'Heurle ,  James M. E. Harper ,  Randy W. Mann ,  Glen L. Miles ,  Donald W. D. Rakowski

发明人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Francois M. d'Heurle ,  James M. E. Harper ,  Randy W. Mann ,  Glen L. Miles ,  Donald W. D. Rakowski

IPC分类号： C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44

CPC分类号： C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665 ,  Y10S148/04 ,  Y10S148/147

摘要： The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10.sup.17 atoms/cm.sup.3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700.degree. C., and more preferably between about 600.degree.-700.degree. C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900.degree. C.

摘要翻译： 形成在半导体晶片上的硅层上形成的金属硅化物层的相变温度降低。 首先，将难熔金属设置在硅层的表面附近，在覆盖难熔金属的层中沉积前体金属，并将晶片加热到足以从前体金属形成金属硅化物的温度。 前体金属可以是难熔金属，优选为钛，钨或钴。 硅层表面的难熔金属的浓度优选小于约1017原子/ cm3。 难熔金属可以是Mo，Co，W，Ta，Nb，Ru或Cr，更优选为Mo或Co。用于形成硅化物的加热步骤在低于约700℃的温度下进行， 更优选在约600℃至700℃之间。任选地，在沉积难熔金属的步骤之后，并且在沉积前体金属层的步骤之前，将晶片退火。 优选地，该退火步骤在至少约900℃的晶片温度下进行。

公开(公告)号：US09029956B2

公开(公告)日：2015-05-12

申请号：US13282299

申请日：2011-10-26

申请人： Randy W. Mann ,  Scott D. Luning

发明人： Randy W. Mann ,  Scott D. Luning

IPC分类号： H01L27/11 ,  G11C11/00 ,  H01L27/02 ,  G11C11/412

CPC分类号： H01L27/0207 ,  G11C11/412 ,  H01L27/1104 ,  Y10S257/903

摘要： A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.

摘要翻译： 提供了一种静态随机存取存储单元，其包括形成在基板上的第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。 第一和第二反相器的每个下拉晶体管驻留在掩埋氧化物层下方的第一区域上，并且具有第一掺杂水平和施加的偏压，为下拉晶体管提供第一电压阈值。 一对通道晶体管耦合第一和第二反相器的单元节点，并且每一个形成在掩埋氧化物层下方的第二区域上，并且具有第二掺杂水平，并且施加的偏置为通路晶体管提供第二电压阈值。 第一电压阈值与提供下拉晶体管和通道晶体管之间的电压阈值控制的第二电压阈值不同。

公开(公告)号：US08907687B2

公开(公告)日：2014-12-09

申请号：US13462942

申请日：2012-05-03

申请人： William McMahon ,  Richard Francis ,  Randy W. Mann

发明人： William McMahon ,  Richard Francis ,  Randy W. Mann

IPC分类号： G01R31/02

CPC分类号： G01R31/30 ,  G11C11/41 ,  G11C29/06

摘要： An integrated circuit device includes at least one test device and a stress generator coupled to the test device and operable to cycle the at least one test device to generate an AC stress. A method for testing an integrated circuit device including at least one test device and a stress generator coupled to the test device includes enabling the stress generator to cycle the at least one test device to generate an AC stress and measuring at least one parameter of the test device to determine an effect of the AC stress.

摘要翻译： 集成电路装置包括耦合到测试装置的至少一个测试装置和应力发生器，并可操作以循环至少一个测试装置以产生AC应力。 一种用于测试包括耦合到测试装置的至少一个测试装置和应力发生器的集成电路装置的方法，包括使所述应力发生器能够循环所述至少一个测试装置以产生AC应力并测量所述测试的至少一个参数 确定AC应力的作用的装置。