公开(公告)号：US10095568B2

公开(公告)日：2018-10-09

申请号：US15498595

申请日：2017-04-27

Applicant: Seagate Technology, LLC

Inventor： Antoine Khoueir ,  Stacey Secatch ,  Kevin Gomez ,  Ryan Goss

IPC: G11C16/04 ,  G06F11/07 ,  G11C16/16 ,  G11C16/34 ,  G11C16/26

Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

公开(公告)号：US09727459B2

公开(公告)日：2017-08-08

申请号：US14466143

申请日：2014-08-22

Applicant: Seagate Technology LLC

Inventor： Antoine Khoueir ,  Ryan James Goss ,  Jon Trantham ,  Kevin Gomez ,  Frank Dropps

IPC: G06F12/06 ,  G11C7/00 ,  G06F3/06 ,  G06F12/00 ,  G11C7/10 ,  G11C16/04 ,  G11C16/26 ,  G11C15/04

CPC classification number: G06F12/06 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0638 ,  G06F2206/1014 ,  G11C7/00 ,  G11C7/1006 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5641

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

公开(公告)号：US20140281280A1

公开(公告)日：2014-09-18

申请号：US13802192

申请日：2013-03-13

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Ryan James Goss ,  Jon D. Trantham ,  Antoine Khoueir ,  David Scott Ebsen ,  Mark Allen Gaertner ,  Kevin Gomez

IPC: G06F3/06

CPC classification number: G06F3/067 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0643 ,  G06F3/0688 ,  G06F2212/7202 ,  G06F2212/7208

Abstract: An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto.

Abstract translation: 一种装置包括能够耦合到主机接口和存储器装置的控制器。 存储器件包括具有不同最小可寻址数据单元尺寸的两个或更多个非分级非易失性存储器单元。 控制器被配置为经由主机接口至少执行存储在存储设备中的数据对象的工作量指示符。 控制器响应于与所述工作负载指示符对应的所选择的存储器单元的最小可寻址数据单元大小对应的数据对象的工作量指示符来选择一个存储器单元。 响应于该数据对象被存储在选择的存储单元中。

公开(公告)号：US10521287B2

公开(公告)日：2019-12-31

申请号：US16153225

申请日：2018-10-05

Applicant: Seagate Technology LLC

Inventor： Antoine Khoueir ,  Stacey Secatch ,  Kevin Gomez ,  Ryan Goss

IPC: G11C16/26 ,  G06F11/07 ,  G11C16/16 ,  G11C16/34 ,  G06F11/10 ,  G11C11/56 ,  G06F12/02 ,  G11C16/04

Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

公开(公告)号：US09489148B2

公开(公告)日：2016-11-08

申请号：US13802192

申请日：2013-03-13

Applicant: Seagate Technology LLC

Inventor： Ryan James Goss ,  Jon D. Trantham ,  Antoine Khoueir ,  David Scott Ebsen ,  Mark Allen Gaertner ,  Kevin Gomez

IPC: G06F3/06

CPC classification number: G06F3/067 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0643 ,  G06F3/0688 ,  G06F2212/7202 ,  G06F2212/7208

Abstract: An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto.

Abstract translation: 一种装置包括能够耦合到主机接口和存储器装置的控制器。 存储器件包括具有不同最小可寻址数据单元尺寸的两个或更多个非分级非易失性存储器单元。 控制器被配置为经由主机接口至少执行存储在存储设备中的数据对象的工作量指示符。 控制器响应于与所述工作负载指示符对应的所选择的存储器单元的最小可寻址数据单元大小对应的数据对象的工作量指示符来选择一个存储器单元。 响应于该数据对象被存储在选择的存储单元中。

公开(公告)号：US20160188226A1

公开(公告)日：2016-06-30

申请号：US14936576

申请日：2015-11-09

Applicant: Seagate Technology LLC

Inventor： Jonathan W. Haines ,  Timothy R. Feldman ,  Wayne H. Vinson ,  Ryan J. Goss ,  Kevin Gomez ,  Mark Allen Gaertner

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

Abstract: An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization.

Abstract translation: 一种示例性方法包括在存储器中提供至少两个数据存储区域，为所述至少两个数据存储区域中的第一个提供第一量的过度供应，以及为所述至少两个数据存储区域中的第二数据存储区域提供第二量的过度供应 数据存储区域，基于数据的特性对数据进行分类，并且基于分类将数据存储在至少两个数据存储区域之一中。

公开(公告)号：US20140244946A1

公开(公告)日：2014-08-28

申请号：US13777137

申请日：2013-02-26

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Antoine Khoueir ,  Jon D. Trantham ,  Kevin Gomez ,  Ara Patapoutian

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F12/0238

Abstract: A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.

Abstract translation: 多个可寻址存储器块各自包括一个或多个交叉点阵列。 每个阵列包括多个非易失性电阻变化存储单元。 控制器被配置为耦合到阵列和主机系统。 控制器被配置为执行从主机系统接收每个具有等于预定逻辑块大小的大小的一个或多个数据对象，并且将一个或多个数据对象存储在相应整数个存储器中的一个或多个存储器中 瓷砖。