公开(公告)号：US10148470B1

公开(公告)日：2018-12-04

申请号：US15674703

申请日：2017-08-11

Applicant: Seagate Technology LLC

Inventor： Belkacem Derras ,  Raman Venkataramani ,  William M. Radich

IPC: H04L25/03 ,  H04B7/0413

Abstract: A method includes receiving a data signal over a multi-input multi-output (MIMO) channel. The method further includes equalizing the data signal, by an adaptive equalizer circuit having an associated target, to provide an equalized output of the data signal. As part of the method, taps of the equalizer circuit and coefficients of the target are estimated. A constraint is imposed on the coefficients of the target as part of the estimation of the coefficients of the target. A similar minimization process is used with constraint imposed on whitening filter taps associated with a DDNP detector in the MIMO channel.

公开(公告)号：US09973354B1

公开(公告)日：2018-05-15

申请号：US15193048

申请日：2016-06-25

Applicant: Seagate Technology LLC

Inventor： William Michael Radich ,  Raman Venkataramani ,  Belkacem Derras ,  Rishi Ahuja

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H04B7/0456 ,  H04L12/26

CPC classification number: H04L25/03006 ,  H04B7/0456 ,  H04L43/028 ,  H04L2025/03624

Abstract: In certain embodiments, an apparatus may comprise a circuit configured to receive a plurality of samples of an input signal. The circuit may update one or more equalizer parameters using partial zero forcing equalization. Further, the circuit may generate an equalized signal based on the plurality of samples of the input signal and the one or more equalizer parameters.

公开(公告)号：US09590803B2

公开(公告)日：2017-03-07

申请号：US14720568

申请日：2015-05-22

Applicant: Seagate Technology LLC

Inventor： Belkacem Derras ,  Raman Venkataramani ,  William Michael Radich

IPC: H04L27/00 ,  H04L7/04 ,  H04L27/227 ,  H04L7/027

CPC classification number: H04L7/048 ,  G11B20/10009 ,  H04L7/0029 ,  H04L7/0062 ,  H04L7/027 ,  H04L25/03 ,  H04L27/2271

Abstract: A digitized signal is processed via an interpolator. The interpolator performs timing adjustment on the digitized signal. The error signal is determined based on a desired signal and the time-adjusted digitized signal. A corrective phase shift of the digitized signal is determined via a least-mean-squared processing block that uses the error and the derivative of a function used by the interpolator. The corrective phase shift is input to the interpolator to perform the timing adjustment.

Abstract translation: 通过内插器处理数字化信号。 内插器对数字化信号执行定时调整。 误差信号根据期望的信号和时间调整的数字化信号确定。 数字化信号的校正相移通过使用误差的内插器所使用的函数的导数的最小均方处理块来确定。 校正相移被输入到内插器以执行定时调整。