公开(公告)号：US20200312772A1

公开(公告)日：2020-10-01

申请号：US16441501

申请日：2019-06-14

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Jine LIU ,  Xiaohe LI ,  Tingting CUI ,  Yuan DING

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.

公开(公告)号：US20200312763A1

公开(公告)日：2020-10-01

申请号：US16441243

申请日：2019-06-14

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Jine LIU ,  Xiaohe LI ,  Tingting CUI ,  Xuhui PENG

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L49/02 ,  H01L25/16 ,  H01L21/56

Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a first metal layer, a second metal layer, and bare chips. The bare chips include first bare chips and second bare chips. First-connecting-posts are formed on a side of the first bare chips and on a side of the second bare chips. The encapsulating layer covers the bare chips and the first-connecting-posts. The first metal layer is disposed on the side of the first-connecting-posts away from the bare chips and includes first capacitor polar plates and conductive parts. The first capacitor polar plates are electrically connected to the first-connecting-posts on the first bare chips, and the conductive parts are electrically connected to the first-connecting-posts on the second bare chips. The second metal layer is disposed on a side of the first metal layer away from the encapsulating layer and includes second capacitor polar plates electrically connected to the conductive parts.

公开(公告)号：US20220270555A1

公开(公告)日：2022-08-25

申请号：US17733534

申请日：2022-04-29

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Xiaohe LI ,  Feng QIN ,  Jine LIU ,  Tingting CUI ,  Baiquan LIN

IPC: G09G3/34 ,  B01L3/00 ,  G01N27/22 ,  H01L27/12 ,  H03K17/687

Abstract: A panel and its drive method are provided. The panel includes: a substrate, an array layer and an electrode array layer, where the array layer is on a side of the substrate; the electrode array layer is on a side of the array layer away from the substrate; and the array layer includes an active layer, a gate metal layer and a source/drain metal layer; the substrate includes a plurality of drive units arranged in an array, a plurality of scan line groups and a plurality of data line groups; the scan line group includes first scan lines and second scan lines adjacent to the first scan lines, extending in a first direction; and the data line group includes first data lines and second data lines adjacent to the first data lines, extending in a second direction.

公开(公告)号：US20210351042A1

公开(公告)日：2021-11-11

申请号：US16913020

申请日：2020-06-26

Applicant: Shanghai Tianma Micro-Electronics Co., Ltd. ,  Shanghai AVIC OPTO Electronics Co.,Ltd.

Inventor： Xuhui PENG ,  Kerui XI ,  Tingting CUI ,  Feng QIN ,  Jie ZHANG

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.

公开(公告)号：US20210334494A1

公开(公告)日：2021-10-28

申请号：US16910840

申请日：2020-06-24

Applicant: Shanghai Tianma Micro-Electronics Co., Ltd. ,  Shanghai AVIC OPTO Electronics Co.,Ltd.

Inventor： Kerui XI ,  Tingting CUI ,  Feng QIN ,  Xuhui PENG ,  Linzhi WANG

IPC: G06K9/00 ,  G06F3/044

Abstract: Fingerprint recognition circuit, fingerprint recognition structure, fingerprint recognition device, display panel, and display device are provided. The circuit includes: a fingerprint recognition driving transistor; a first capacitor; a driving signal input terminal; and a sensing signal output terminal. The first capacitor has a terminal electrically connected to a gate of the fingerprint recognition driving transistor and another terminal electrically connected to a ground. The driving signal input terminal is electrically connected to an input terminal of the fingerprint recognition driving transistor. An output terminal of the fingerprint recognition driving transistor is electrically connected to the sensing signal output terminal.

公开(公告)号：US20210280525A1

公开(公告)日：2021-09-09

申请号：US17330236

申请日：2021-05-25

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Jine LIU ,  Xiaohe LI ,  Tingting CUI

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/544 ,  H01L23/00

Abstract: Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

公开(公告)号：US20200328159A1

公开(公告)日：2020-10-15

申请号：US16457290

申请日：2019-06-28

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Jine LIU ,  Xiaohe LI ,  Tingting CUI

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/544 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A panel-level chip device and a packaging method for forming the panel-level chip device are provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

公开(公告)号：US20200316591A1

公开(公告)日：2020-10-08

申请号：US16457939

申请日：2019-06-29

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Xiaohe LI ,  Feng QIN ,  Jine LIU ,  Tingting CUI ,  Baiquan LIN

IPC: B01L3/00 ,  H01L27/12 ,  H03K17/687 ,  G01N27/22 ,  G09G3/34

Abstract: A drive circuit and its drive method, and a panel and its drive method are provided. The drive circuit includes a step-up unit, a plurality of signal input terminals and a signal output terminal. The step-up unit includes a first module, a second module and a first capacitor. The first module is configured to transmit a signal of a third signal input terminal to a first electrode of the first capacitor. The second module is configured to transmit a signal of a fourth signal input terminal to a second electrode of the first capacitor at a first time period which generates a voltage difference between two electrodes of the first capacitor, and to transmit the signal of the fourth signal input terminal to the second electrode of the first capacitor at a second time period which further increases a signal of the first electrode of the first capacitor.

公开(公告)号：US20200312779A1

公开(公告)日：2020-10-01

申请号：US16456392

申请日：2019-06-28

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Jine LIU ,  Xiaohe LI ,  Tingting CUI

IPC: H01L23/544 ,  H01L23/48 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L21/02

Abstract: Chip package method and chip package structure are provided. The chip package method includes: providing a transparent substrate including a first side and a second side; coating the first side of the transparent substrate with an organic polymer material layer; depositing a protective layer on the organic polymer material layer; forming alignment parts on the protective layer; attaching a plurality of chips including metal pins; forming an encapsulating layer on the protective layer; polishing the encapsulating layer to expose the metal pins; forming a first insulating layer; forming first through holes in the first insulating layer; forming metal parts extending along sidewalls of the first through holes; and irradiating the second side of the transparent substrate by a laser to lift off the transparent substrate. The metal parts are insulated from each other and electrically connected to the metal pins.