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    METHOD TO IMPROVE TRANSISTOR TOX USING SI RECESSING WITH NO ADDITIONAL MASKING STEPS
    11.
    发明申请
    METHOD TO IMPROVE TRANSISTOR TOX USING SI RECESSING WITH NO ADDITIONAL MASKING STEPS 审中-公开
    使用无附加掩蔽步骤的方法来改善晶状体毒素的方法

    公开(公告)号：US20110027954A1

    公开(公告)日：2011-02-03

    申请号：US12900821

    申请日：2010-10-08

    申请人： Borna Obradovic ,  Shashank S. Ekbote

    发明人： Borna Obradovic ,  Shashank S. Ekbote

    IPC分类号： H01L21/335 ,  H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/7848

    摘要： A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.

    摘要翻译： 提供一种形成晶体管器件的方法，其中栅极结构形成在第一导电类型的半导体本体上。 门结构被形成为包括其上的保护盖并且限定与其横向相邻的源/漏区。 在栅极结构和源极/漏极区域中进行第二导电类型的第一注入。 半导体本体被蚀刻以形成基本上对准栅极结构的凹槽，其中第一注入从源极/漏极区域移除。 通过选择性外延生长植入或生长源极/漏极区域。

    METHOD TO IMPROVE TRANSISTOR TOX USING SI RECESSING WITH NO ADDITIONAL MASKING STEPS
    12.
    发明申请
    METHOD TO IMPROVE TRANSISTOR TOX USING SI RECESSING WITH NO ADDITIONAL MASKING STEPS 有权
    使用无附加掩蔽步骤的方法来改善晶状体毒素的方法

    公开(公告)号：US20090093095A1

    公开(公告)日：2009-04-09

    申请号：US11868787

    申请日：2007-10-08

    申请人： Borna Obradovic ,  Shashank S. Ekbote

    发明人： Borna Obradovic ,  Shashank S. Ekbote

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/7848

    摘要： A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.

    摘要翻译： 提供一种形成晶体管器件的方法，其中栅极结构形成在第一导电类型的半导体本体上。 门结构被形成为包括其上的保护盖并且限定与其横向相邻的源/漏区。 在栅极结构和源极/漏极区域中进行第二导电类型的第一注入。 半导体本体被蚀刻以形成基本上对准栅极结构的凹槽，其中第一注入从源极/漏极区域移除。 通过选择性外延生长植入或生长源极/漏极区域。

    Mitigation of gate to contact capacitance in CMOS flow
    13.
    发明申请
    Mitigation of gate to contact capacitance in CMOS flow 有权
    栅极接触电容在CMOS流中的缓解

    公开(公告)号：US20080230815A1

    公开(公告)日：2008-09-25

    申请号：US11726253

    申请日：2007-03-21

    申请人： Shashank Sureshchandra Ekbote ,  Borna Obradovic ,  Lindsey Hall ,  Craig Huffman ,  Ajith Varghese

    发明人： Shashank Sureshchandra Ekbote ,  Borna Obradovic ,  Lindsey Hall ,  Craig Huffman ,  Ajith Varghese

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7833 ,  H01L21/76804 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/6659 ,  Y02P80/30

    摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.

    摘要翻译： 主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。 单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。 因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。 因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。 这种电容至少是不利的，因为它可以抑制晶体管的切换速度。 因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。

    Method to improve transistor Tox using high-angle implants with no additional masks
    16.
    发明授权
    Method to improve transistor Tox using high-angle implants with no additional masks 有权
    使用不带附加掩模的高角度植入物来改善晶体管Tox的方法

    公开(公告)号：US07727838B2

    公开(公告)日：2010-06-01

    申请号：US11829181

    申请日：2007-07-27

    申请人： Borna Obradovic ,  Shashank S. Ekbote

    发明人： Borna Obradovic ,  Shashank S. Ekbote

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28035 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body therebetween. The method further includes performing an angled implant into the gate structure, wherein the shadowing structure substantially blocks dopant from the angled implant from implanting into the active area, and performing a source/drain implant into the gate structure and the active area.

    摘要翻译： 形成集成电路的方法包括在半导体本体上形成栅极结构，并且在半导体本体上与栅极结构横向间隔开形成阴影结构，由此在半导体本体之间限定有效区域。 所述方法还包括对所述栅极结构执行成角度的注入，其中所述阴影结构基本上阻止来自所述成角度植入物的掺杂物注入到所述有源区域中，以及对所述栅极结构和所述有源区域进行源极/漏极注入。

    Characterization and modeling of ferroelectric capacitors
    19.
    发明授权
    Characterization and modeling of ferroelectric capacitors 有权
    铁电电容器的表征和建模

    公开(公告)号：US08170858B2

    公开(公告)日：2012-05-01

    申请号：US12394849

    申请日：2009-02-27

    申请人： Borna Obradovic ,  Keith Green

    发明人： Borna Obradovic ,  Keith Green

    IPC分类号： G06F17/50 ,  G06G7/62 ,  G06G7/48

    CPC分类号： G06F17/5036

    摘要： Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the polarization of each of the domains, as weighted by the weighting function. A time-dependent factor can be included in the polarization expression evaluated for each domain, to include the effect of relaxation. The effects of longer-term mechanisms, such as imprint, can be modeled by deriving a probability distribution function for the domains after an accelerated stress.

    摘要翻译： 包括铁电电容器型号的电子电路仿真。 铁电电容器的模型包括多畴铁电电容器，其中每个畴与正矫顽电压和负矫顽电压相关联。 定义正矫顽电压和负矫顽电压的概率分布函数，从而确定具有矫顽电压的域的分布的加权函数。 通过评估加权函数加权的每个域的极化来评估铁电电容器的电气行为。 时间依赖因子可以包括在为每个域评估的极化表达式中，以包括放松的效果。 长期机制（如印记）的影响可以通过推导加速应力后的域的概率分布函数来建模。

    Mitigation of gate to contact capacitance in CMOS flow
    20.
    发明授权
    Mitigation of gate to contact capacitance in CMOS flow 有权
    栅极接触电容在CMOS流中的缓解

    公开(公告)号：US08119470B2

    公开(公告)日：2012-02-21

    申请号：US11726253

    申请日：2007-03-21

    申请人： Shashank Sureshchandra Ekbote ,  Borna Obradovic ,  Lindsey Hall ,  Craig Huffman ,  Ajith Varghese

    发明人： Shashank Sureshchandra Ekbote ,  Borna Obradovic ,  Lindsey Hall ,  Craig Huffman ,  Ajith Varghese

    IPC分类号： H01L21/338 ,  H01L21/336 ,  H01L21/4763

    CPC分类号： H01L29/7833 ,  H01L21/76804 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/6659 ,  Y02P80/30

    摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.

    摘要翻译： 主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。 单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。 因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。 因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。 这种电容至少是不利的，因为它可以抑制晶体管的切换速度。 因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。