公开(公告)号：US08311059B2

公开(公告)日：2012-11-13

申请号：US11222401

申请日：2005-09-07

申请人： James B. Williams

发明人： James B. Williams

IPC分类号： H04J3/16 ,  H04J3/22

CPC分类号： H04L69/16 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9094 ,  H04L69/12 ,  H04L69/161

摘要： An apparatus and method is disclosed for reducing the computational overhead incurred by a host processor during packet processing and improving network performance by adding additional functionality to a Network Interface Controller (NIC). Under certain circumstances the NIC coalesces multiple receive packets into a single coalesced packet stored within a coalesce buffer in host memory. The coalesced packet includes an Ethernet header, a coalesced Internet Protocol (IP) header, a coalesced Transmission Control Protocol (TCP) header, and a coalesced TCP payload containing the TCP payloads of the multiple receive packets. By coalescing received packets into fewer larger coalesced packets within the host memory, the host software needed to process a receive packet will be invoked less often, meaning that less processor overhead is incurred in the host.

摘要翻译： 公开了一种用于在分组处理期间减少由主处理器产生的计算开销并通过向网络接口控制器（NIC）添加附加功能来提高网络性能的装置和方法。 在某些情况下，NIC将多个接收分组合并成存储在主机存储器中的合并缓冲器内的单个合并分组。 合并的分组包括以太网报头，合并的因特网协议（IP）报头，合并的传输控制协议（TCP）报头，以及包含多个接收分组的TCP有效载荷的合并的TCP有效载荷。 通过将接收到的数据包合并到主机存储器内较少的较大的合并数据包中，处理接收数据包所需的主机软件将被更少地调用，这意味着在主机中会产生较少的处理器开销。

公开(公告)号：US08214531B2

公开(公告)日：2012-07-03

申请号：US10280503

申请日：2002-10-24

申请人： Bino J. Sebastian ,  Richard F. Prohaska ,  James B. Williams

发明人： Bino J. Sebastian ,  Richard F. Prohaska ,  James B. Williams

IPC分类号： G06F15/16 ,  G06F11/00

CPC分类号： H04L41/0816 ,  H04L41/0856 ,  H04L69/10 ,  H04L69/12

摘要： Systems and techniques to synchronize network configuration for a hardware accelerated network protocol. According to an aspect, a network configuration record is maintained for a hardware-accelerated network-protocol device, a network configuration store is monitored to identify a network configuration change, and the hardware-accelerated network-protocol device is reconfigured, in response to the identified network configuration change, based on the network configuration record and the network configuration change.

摘要翻译： 用于硬件加速网络协议同步网络配置的系统和技术。 根据一方面，为硬件加速网络协议设备维护网络配置记录，监视网络配置存储以识别网络配置改变，并且响应于所述硬件加速网络协议设备重新配置硬件加速网络协议设备 识别网络配置更改，根据网络配置记录和网络配置更改。

公开(公告)号：US20080083193A1

公开(公告)日：2008-04-10

申请号：US11865244

申请日：2007-10-01

申请人： Timothy B. McGlinchy ,  James B. Williams ,  Robert R. Shepherd ,  Brady S. Jacot ,  David F. Lewis

发明人： Timothy B. McGlinchy ,  James B. Williams ,  Robert R. Shepherd ,  Brady S. Jacot ,  David F. Lewis

IPC分类号： E04G19/00

CPC分类号： B29C37/04 ,  B29C65/02 ,  B29C66/1142 ,  B29C66/1162 ,  B29C66/5241 ,  B29C66/5243 ,  B29C66/52431 ,  B29K2101/12 ,  B29L2031/005 ,  E06B3/9608 ,  Y10T408/52

摘要： A window processing system is disclosed for fabricating window frames. A welding station has welding heads to weld or fuse vinyl frame parts together. The frames are taken to a cleaning station having a number of cleaning heads that are independently actuated to move into a position relative selected portions of the window frame to clean off burrs, weld beads etc from the welded window frame. The cleaning process involves both training of a controller to recognize certain frame profiles and a compensation process for adjusting the cleaning process for individual variations in the frame that occur during fabrication. Real-time cleaning involves coupling a visual sensor to a moving support that also supports a cleaning tool.

摘要翻译： 公开了一种用于制造窗框的窗口处理系统。 焊接站具有焊接头以将乙烯基框架部件焊接或熔接在一起。 框架被带到具有多个清洁头的清洁站，清洁头被独立地致动以移动到相对于窗框的选定部分的位置，以从焊接的窗框中清除毛刺，焊缝等。 清洁过程涉及控制器的训练以识别某些框架轮廓以及用于调整在制造期间发生的框架中的各个变化的清洁过程的补偿过程。 实时清洁涉及将视觉传感器耦合到还支持清洁工具的移动支架。

公开(公告)号：US07012918B2

公开(公告)日：2006-03-14

申请号：US10396985

申请日：2003-03-24

申请人： James B. Williams

发明人： James B. Williams

IPC分类号： H04L12/56

CPC分类号： H04L49/9063 ,  H04L49/90

摘要： A system comprising a host and a network interface card or host bus adapter. The host is configured to perform transport protocol processing. The network interface card is configured to directly place data from a network into a buffer memory in the host.

摘要翻译： 一种包括主机和网络接口卡或主机总线适配器的系统。 主机被配置为执行传输协议处理。 网络接口卡被配置为直接将数据从网络放置到主机中的缓冲存储器中。

公开(公告)号：US06174540B1

公开(公告)日：2001-01-16

申请号：US09152775

申请日：1998-09-14

申请人： James B. Williams ,  Rey T. Chern

发明人： James B. Williams ,  Rey T. Chern

IPC分类号： A61F202

CPC分类号： A61K31/7048 ,  A61K9/0019 ,  A61K47/14 ,  A61K47/44

摘要： Long-acting injectable formulations are formed from a) a therapeutic agent selected from insecticides, acaricides, parasiticides, growth enhancers or oil-soluble NSAIDs, b) hydrogenated castor oil, and c) a hydrophobic carrier comprising i) triacetin, benzyl benzoate, ethyl oleate, or a combination thereof, and ii) acylated monoglycerides, propyl dicaprylates/dicaprates, caprylic/capric acid triglycerides or a combination thereof.

摘要翻译： 长效注射制剂由a）选自杀虫剂，杀螨剂，杀寄生虫剂，生长增强剂或油溶性非甾体类抗炎药的治疗剂形成，b）氢化蓖麻油，和c）疏水性载体，其包含i）三醋精，苯甲酸苄酯， 油酸酯或其组合，和ii）酰化单甘油酯，二辛酸丙酯/二癸酸酯，辛酸/癸酸甘油三酸酯或其组合。

公开(公告)号：US5516761A

公开(公告)日：1996-05-14

申请号：US333936

申请日：1994-11-03

申请人： Hoo-Kyun Choi ,  James B. Williams

发明人： Hoo-Kyun Choi ,  James B. Williams

IPC分类号： A01N43/90 ,  A61K9/00 ,  A61K31/70

CPC分类号： A61K9/0017 ,  A01N43/90 ,  Y10S514/947

摘要： There is disclosed a topical multiple-point-application formulation containing a solution of a polymeric material and an avermectin compound (active ingredient) which has been discovered to provide superior efficacy against ectoparasites, such as fleas and ticks and endoparasites such as nematodes and heartworms, when compared to conventional formulations. The formulation contains the avermectin active ingredient and up to 50% of the polymeric material.

摘要翻译： 公开了一种含有聚合材料和除虫菌素化合物（活性成分）的溶液的局部多点施用制剂，其被发现提供了对外寄生物例如跳蚤和蜱和内寄生虫如线虫和心丝虫的优异功效， 当与常规制剂相比时。 制剂含有除虫菌素活性成分和高达50％的聚合物材料。

公开(公告)号：US4940929A

公开(公告)日：1990-07-10

申请号：US370611

申请日：1989-06-23

申请人： James B. Williams

发明人： James B. Williams

IPC分类号： H02M1/00 ,  H02M1/42 ,  H02M3/156

CPC分类号： H02M1/4225 ,  H02M3/156 ,  Y02B70/126

摘要： An AC to DC converter comprises a bridge rectifier followed by a boost circuit. The boost circuit includes an inductor, diode and load capacitor in series and a shunting switch connected to shunt the diode and load capacitor. The control circuit for switching the shunting switch comprises a differential circuit, a multiplier and a duty cycle generator in a feedback loop which maintains a constant output voltage on the capacitor. To eliminate the response to ripple on the output voltage, the differential circuit does not respond to voltages within a dead band.

摘要翻译： AC到DC转换器包括桥式整流器，随后是升压电路。 升压电路包括串联的电感器，二极管和负载电容器以及分流开关，用于分流二极管和负载电容器。 用于切换分流开关的控制电路包括在反馈环路中的差分电路，乘法器和占空比发生器，其在电容器上保持恒定的输出电压。 为了消除对输出电压纹波的响应，差分电路对死区内的电压无响应。

公开(公告)号：US07953876B1

公开(公告)日：2011-05-31

申请号：US10651426

申请日：2003-08-28

申请人： Harold E. Roman ,  James B. Williams

发明人： Harold E. Roman ,  James B. Williams

IPC分类号： G06F15/16

CPC分类号： H04L69/16 ,  H04L69/163

摘要： A method and system comprising a host system and a host bus adapter (HBA). The HBA is configured to handle a Virtual Interface and Transmission Control Protocol (TCP)/Internet Protocol (IP) processing for applications running on the host system.

摘要翻译： 一种包括主机系统和主机总线适配器（HBA）的方法和系统。 HBA被配置为处理在主机系统上运行的应用的虚拟接口和传输控制协议（TCP）/因特网协议（IP）处理。

公开(公告)号：US5991818A

公开(公告)日：1999-11-23

申请号：US67533

申请日：1998-04-27

申请人： James B. Williams

发明人： James B. Williams

IPC分类号： G06F13/00 ,  H04L12/56

CPC分类号： H04L49/901 ,  H04L49/90 ,  H04L49/9057

摘要： A system comprises a plurality of devices which communicate over a network. At least one of the devices transmits information to at least one other of the devices in information messages over a virtual circuit established therebetween using the network. The other device can transmit information concerning, for example, predetermined conditions in the other device in connection with the virtual circuit using signalling messages, which are transmitted by the other device over the virtual circuit to the one device. The one device includes a plurality of mailboxes associated with the virtual circuit, and the other device, that is, the device that is to transmit signalling messages, includes a transmit signal queue including a plurality of entries each associated with one of the mailboxes. A processor on the other device, to enable transmission of a signalling message including the condition information to be transferred to a mailbox, loads the condition information to be transferred into the transmit signal queue entry associated with the mailbox. The other device, in turn, transmits the signalling message to the one device, which loads the condition information in the appropriate mailbox. A processor on the one device retrieves the condition information from the mailbox to determine the condition information as communicated thereto by the other device.

摘要翻译： 系统包括通过网络进行通信的多个设备。 至少一个设备通过使用网络在其间建立的虚拟电路上的信息消息中的至少一个设备传送信息。 另一个设备可以使用信令消息来传送关于另一个设备中与预定条件有关的信息，该信息消息是由另一个设备通过虚拟电路传送到该设备的。 一个设备包括与虚拟电路相关联的多个邮箱，而另一个设备，即要发送信令消息的设备，包括包括与每个邮箱之一相关联的多个条目的发送信号队列。 在另一设备上的处理器，为了能够发送包括要传送到邮箱的条件信息的信令消息，将要传送的条件信息加载到与邮箱相关联的发送信号队列条目中。 另一个设备又将信令消息发送到一个设备，该设备将条件信息加载到适当的邮箱中。 一个设备上的处理器从邮箱检索条件信息，以确定另一个设备传达的条件信息。

公开(公告)号：US5649157A

公开(公告)日：1997-07-15

申请号：US413672

申请日：1995-03-30

申请人： James B. Williams

发明人： James B. Williams

IPC分类号： G06F13/18

CPC分类号： G06F13/18

摘要： A memory controller receives reads, memory writes, and cache writes. A pending read is selected and issued to memory. When a response is received from memory, all cache writes are checked to determine whether any correspond to the pending read. If there is a corresponding cache write, the data from the corresponding cache write is used to respond to the pending read. Otherwise, prior memory writes arc checked to determine whether any correspond to the pending read. If there is a corresponding prior memory write, the data from the corresponding prior memory write is used to respond to the pending read. A coherency check from associated caches may also be performed, and the appropriate data returned to the processor that requested the read. Three queues may control the order in which memory access is performed. A read queue that contains read requests is typically given highest priority, and therefore reads are generally serviced first. A wait queue contains read requests and memory write requests, and is incremented to the pending read before the pending read is completed. As the wait queue is incremented, memory writes from the wait queue are entered onto a ready queue. Each request retrieved from the wait queue is checked against pending requests in the ready queue. Cache writes are entered directly onto the ready queue. When either a conflict is detected for the pending ready, or when the ready queue contains a certain amount of requests, the ready queue is flushed.

摘要翻译： 存储器控制器接收读取，存储器写入和高速缓存写入。 选择待处理的读取并发布到内存。 当从存储器接收到响应时，检查所有高速缓存写入以确定是否对应于待处理读取。 如果存在对应的缓存写入，则来自相应缓存写入的数据用于响应待处理读取。 否则，先前存储器写入被检查以确定是否对应于待处理读取。 如果存在对应的先前存储器写入，则来自相应的先前存储器写入的数据用于响应待处理读取。 还可以执行来自关联高速缓存的一致性检查，并且将适当的数据返回到请求读取的处理器。 三个队列可以控制执行存储器访问的顺序。 包含读取请求的读取队列通常被赋予最高优先级，因此读取通常首先被服务。 等待队列包含读取请求和内存写入请求，并在挂起的读取完成之前增加到待处理的读取。 随着等待队列递增，来自等待队列的内存写入被输入到可用队列中。 从待机队列中的待处理请求检查从等待队列检索的每个请求。 缓存写入直接输入到就绪队列中。 当检测到待处理准备就绪的冲突，或者当就绪队列包含一定量的请求时，就会清除就绪队列。