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    Semiconductor integrated circuit device
    11.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08072799B2

    公开(公告)日：2011-12-06

    申请号：US12662029

    申请日：2010-03-29

    申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

    发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

    摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

    摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

    Semiconductor integrated circuit device
    12.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07477537B2

    公开(公告)日：2009-01-13

    申请号：US11504079

    申请日：2006-08-15

    申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

    发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

    摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

    摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

    Semiconductor integrated circuit device
    13.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07420834B2

    公开(公告)日：2008-09-02

    申请号：US11504077

    申请日：2006-08-15

    申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

    发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

    摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

    摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR
    17.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR 审中-公开
    半导体集成电路及其制造方法

    公开(公告)号：US20080143423A1

    公开(公告)日：2008-06-19

    申请号：US11943095

    申请日：2007-11-20

    申请人： Shigenobu Komatsu ,  Kenichi Osada ,  Masanao Yamaoka ,  Koichiro Ishibashi

    发明人： Shigenobu Komatsu ,  Kenichi Osada ,  Masanao Yamaoka ,  Koichiro Ishibashi

    IPC分类号： H03K3/01 ,  H01L21/8238

    CPC分类号： H01L27/092 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203 ,  H03K19/0027 ,  H03K19/00315

    摘要： The present invention is directed to realize high manufacture yield and compensate variations in threshold voltage of a MOS transistor with small overhead. A semiconductor integrated circuit includes a CMOS circuit for processing an input signal in an active mode, a control switch, and a control memory. The control switch supplies a pMOS body bias voltage and an nMOS body bias voltage to an N well in a pMOS transistor and a P well in an nMOS transistor, respectively, in the CMOS circuit. The control memory stores control information indicating whether or not the pMOS body bias voltage and the nMOS body bias voltage are supplied from the control switch to the N well in the pMOS transistor and the P well in the nMOS transistor, respectively, in the CMOS circuit in the active mode.

    摘要翻译： 本发明旨在实现高制造成品率并补偿具有较小开销的MOS晶体管的阈值电压的变化。 半导体集成电路包括用于处理活动模式中的输入信号的CMOS电路，控制开关和控制存储器。 控制开关分别向CMOS电路中的nMOS晶体管中的pMOS晶体管和P阱中的N阱施加pMOS体偏置电压和nMOS体偏置电压。 控制存储器存储指示pMOS体偏置电压和nMOS体偏置电压是否从控制开关提供到CMOS电路中的nMOS晶体管中的pMOS晶体管和P阱中的N阱的控制信息 处于活动模式。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    18.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20080174359A1

    公开(公告)日：2008-07-24

    申请号：US11942939

    申请日：2007-11-20

    申请人： Kenichi OSADA ,  Masanao Yamaoka ,  Shigenobu Komatsu

    发明人： Kenichi OSADA ,  Masanao Yamaoka ,  Shigenobu Komatsu

    IPC分类号： H03K3/01

    CPC分类号： H03K19/0008 ,  H03K2217/0018

    摘要： A substrate bias technique is used in an active mode enabling a high yield, and an operating consumption power and the fluctuation of a signal delay in signal processing are reduced in the active mode. The additional PMOS and NMOS of the additional capacitance circuit are produced in the same production process as the PMOSs and the NMOSs of the CMOS circuits. The gate capacitance of the additional PMOS is coupled between the power supply wiring and the N well and the gate capacitance of the additional NMOS is coupled between the ground wiring and the P well. The noise on the power supply wiring is transmitted to the N well through the gate capacitance and the noise on the ground wiring is transmitted to the P well through the gate capacitance. The fluctuation of noise on the substrate bias voltage between the source and the well of PMOS and NMOS of the CMOS circuits is reduced.

    摘要翻译： 在有源模式中使用基板偏压技术，能够实现高产量，并且在活动模式中降低了操作消耗功率和信号处理中的信号延迟的波动。 附加电容电路的附加PMOS和NMOS在与CMOS电路的PMOS和NMOS的生产过程相同的情况下生产。 附加PMOS的栅极电容耦合在电源布线和N阱之间，附加NMOS的栅极电容耦合在接地布线和P阱之间。 电源线上的噪声通过栅极电容传输到N阱，接地线上的噪声通过栅极电容传输到P阱。 CMOS电路的PMOS和NMOS的源极和阱之间的衬底偏置电压上的噪声波动减小。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR
    19.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR 有权
    半导体集成电路及其制造方法

    公开(公告)号：US20100027322A1

    公开(公告)日：2010-02-04

    申请号：US12563231

    申请日：2009-09-21

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/417

    摘要： In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

    摘要翻译： 在本发明中，实现了高制造成品率，并补偿了CMOS.SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据测定结果分别被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS.SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

    Semiconductor integrated circuit device
    20.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20070297270A1

    公开(公告)日：2007-12-27

    申请号：US11812193

    申请日：2007-06-15

    申请人： Shigenobu Komatsu ,  Masanao Yamaoka

    发明人： Shigenobu Komatsu ,  Masanao Yamaoka

    IPC分类号： G11C8/00 ,  G11C11/00

    CPC分类号： G11C8/08 ,  G11C8/18 ,  G11C11/412

    摘要： The present invention provides a technique capable of achieving area reduction on a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like. By providing a configuration including a single port memory, data latch circuit for plural ports, a selector for selecting a port to be connected to the single port memory, a time sharing control signal generating circuit and the like, in which an operation termination signal inside the single port memory (a word line rising signal, a sense amplifier driving signal for data read or the like) is inputted to the time sharing control signal generating circuit to produce a port switching control signal and an operation control signal for the single port memory, a time sharing virtual multi port memory with a reduced area can be realized which requires no clock generating circuit for time sharing control newly.

    摘要翻译： 本发明提供一种能够在安装有时间分配虚拟多端口存储器等的半导体集成电路装置上实现面积缩小的技术。 通过提供包括单端口存储器，用于多个端口的数据锁存电路，用于选择要连接到单端口存储器的端口的选择器，时间共享控制信号生成电路等，其中内部的操作终止信号 将单端口存储器（字线上升信号，用于数据读取的读出放大器驱动信号等）输入到时间共享控制信号发生电路，以产生用于单端口存储器的端口切换控制信号和操作控制信号 可以实现具有减小面积的虚拟多端口存储器的时间分配，这不需要新的时间分配控制的时钟发生电路。