公开(公告)号：US08072799B2

公开(公告)日：2011-12-06

申请号：US12662029

申请日：2010-03-29

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US07477537B2

公开(公告)日：2009-01-13

申请号：US11504079

申请日：2006-08-15

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US07420834B2

公开(公告)日：2008-09-02

申请号：US11504077

申请日：2006-08-15

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US07113421B2

公开(公告)日：2006-09-26

申请号：US11127286

申请日：2005-05-12

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

公开(公告)号：US20120044775A1

公开(公告)日：2012-02-23

申请号：US13317846

申请日：2011-10-31

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C7/00

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

摘要翻译： 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US20100188887A1

公开(公告)日：2010-07-29

申请号：US12662029

申请日：2010-03-29

申请人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

发明人： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

公开(公告)号：US20130026580A1

公开(公告)日：2013-01-31

申请号：US13559461

申请日：2012-07-26

申请人： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

发明人： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

IPC分类号： H01L27/11

CPC分类号： H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

摘要： A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

摘要翻译： 一种具有SRAM的半导体器件，包括：第一晶体管和第五晶体管设置在其中的单片第一有源区; 与第一有源区分离的第二有源区，其中设置第二晶体管; 其中设置第三晶体管和第六晶体管的单片第三有源区; 以及与第三有源区分离的第四有源区，其中设置第四晶体管。 每个驱动晶体管分为第一晶体管和第二晶体管（或第三晶体管和第四晶体管），并且这些驱动晶体管设置在不同的有源区域上。

公开(公告)号：US08957459B2

公开(公告)日：2015-02-17

申请号：US13559461

申请日：2012-07-26

申请人： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

发明人： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

IPC分类号： H01L27/092 ,  H01L27/11 ,  H01L27/02 ,  G11C11/412

CPC分类号： H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

摘要： A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

摘要翻译： 一种具有SRAM的半导体器件，包括：第一晶体管和第五晶体管设置在其中的单片第一有源区; 与第一有源区分离的第二有源区，其中设置第二晶体管; 其中设置第三晶体管和第六晶体管的单片第三有源区; 以及与第三有源区分离的第四有源区，其中设置第四晶体管。 每个驱动晶体管分为第一晶体管和第二晶体管（或第三晶体管和第四晶体管），并且这些驱动晶体管设置在不同的有源区域上。

公开(公告)号：US20050052925A1

公开(公告)日：2005-03-10

申请号：US10927052

申请日：2004-08-27

申请人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

发明人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

IPC分类号： G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C11/41 ,  G11C11/413 ,  G11C7/00

CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

摘要翻译： 功率控制部的MOS晶体管的待机时的漏电流急剧下降，能够实现消耗功率的降低。 存储器模块具有功率控制部分。 当没有选择任何存储器垫时，功率控制部分将电源电压停止到未选择的存储器垫，字驱动器，输入输出电路，控制电路和输出电路。 在存储器模块的待机时，功率控制部分停止对功率控制部分，控制电路，预解码器电路和输入电路的电源。 以这种方式，可以显着降低在待机时功率控制部分的MOS晶体管的漏电流。

公开(公告)号：US20080247258A1

公开(公告)日：2008-10-09

申请号：US12117804

申请日：2008-05-09

申请人： Noriyoshi WATANABE ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

发明人： Noriyoshi WATANABE ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

摘要翻译： 功率控制部的MOS晶体管的待机时的漏电流急剧下降，能够实现消耗功率的降低。 存储器模块具有功率控制部分。 当没有选择任何存储器垫时，功率控制部分将电源电压停止到未选择的存储器垫，字驱动器，输入输出电路，控制电路和输出电路。 在存储器模块的待机时，功率控制部分停止对功率控制部分，控制电路，预解码器电路和输入电路的电源。 以这种方式，可以显着降低在待机时功率控制部分的MOS晶体管的漏电流。