公开(公告)号：US08261214B2

公开(公告)日：2012-09-04

申请号：US12630048

申请日：2009-12-03

Applicant: Shimon Maeda ,  Masahiro Miyairi ,  Soichi Inoue

Inventor： Shimon Maeda ,  Masahiro Miyairi ,  Soichi Inoue

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.

Abstract translation: 每个图形被认为是在第一距离处彼此相邻的图案的节点和节点之间的图形被生成，每个图案被分成两种类型，使得对应于 边缘两端的节点是彼此不同的类型，分类结果通过将由边缘连接的每个节点簇中的模式或通过该节点连接的每个节点集合的边缘分组，并将每种类型的 在一对图案中属于与一种图案相同的组合的图案，其分为相同类型并且分别属于彼此相邻的第二距离的不同组，并且基于图案布局图 对正确的分类结果。

公开(公告)号：US07966580B2

公开(公告)日：2011-06-21

申请号：US12186244

申请日：2008-08-05

Applicant: Shimon Maeda

Inventor： Shimon Maeda

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different model parameter; performing a simulation of the mask pattern by using each of the process models to predict a plurality of model patterns; calculating a difference in dimension between the test pattern and each of the model patterns; extracting a model pattern in which the difference in dimension from the test pattern is within a scope of specification from the model patterns; and specifying the process model, which predicts the extracted model pattern, as the mask pattern.

Abstract translation: 根据本发明的实施例的工艺模型生成方法包括：通过使形成在其上的掩模图案的测试掩模曝光来在要处理的膜上形成测试图案; 产生具有不同模型参数的多个过程模型; 通过使用每个过程模型来执行掩模图案的模拟以预测多个模型模式; 计算测试图案与每个模型图案之间的尺寸差异; 提取其中尺寸与测试图案的差异在模型范围内的模型模式; 并指定将所提取的模型模式预测为过程模型作为掩模图案。

公开(公告)号：US20090077530A1

公开(公告)日：2009-03-19

申请号：US12269705

申请日：2008-11-12

Applicant: TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

Inventor： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

公开(公告)号：US20090077529A1

公开(公告)日：2009-03-19

申请号：US12269687

申请日：2008-11-12

Applicant: TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

Inventor： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

Abstract translation: 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此相对。

公开(公告)号：US08785329B2

公开(公告)日：2014-07-22

申请号：US13728495

申请日：2012-12-27

Applicant: Shimon Maeda ,  Kenji Konomi

Inventor： Shimon Maeda ,  Kenji Konomi

IPC: H01L21/00

CPC classification number: H01L21/02318 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/0271 ,  H01L21/32139

Abstract: In a method for forming a pattern according to an embodiment, a first guide pattern and a second guide pattern for induced self organization of a DSA material are formed on substrate. On a first DSA condition, a first phase-separated pattern having regularity with respect to the first guide pattern is formed, and a first pattern is formed by processing the lower layer side. Subsequently, on a second DSA condition, a second phase-separated pattern having regularity with respect to the second guide pattern is formed, and a second pattern is formed by processing the lower layer side.

Abstract translation: 在根据实施例的形成图案的方法中，在基底上形成用于DSA材料的诱导自组织的第一引导图案和第二引导图案。 在第一DSA条件下，形成相对于第一引导图案具有规则性的第一相分离图案，并且通过处理下层侧形成第一图案。 随后，在第二DSA条件下，形成相对于第二引导图案具有规则性的第二相分离图案，并且通过处理下层侧形成第二图案。

公开(公告)号：US20120198396A1

公开(公告)日：2012-08-02

申请号：US13237854

申请日：2011-09-20

Applicant: Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

Inventor： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

IPC: G06F17/50

CPC classification number: H01L22/20 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.

Abstract translation: 根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。 根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时， 在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

公开(公告)号：US07949967B2

公开(公告)日：2011-05-24

申请号：US12269705

申请日：2008-11-12

Applicant: Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

Inventor： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

Abstract translation: 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此。

公开(公告)号：US07917871B2

公开(公告)日：2011-03-29

申请号：US12180244

申请日：2008-07-25

Applicant: Sachiko Kobayashi ,  Suigen Kyoh ,  Shimon Maeda

Inventor： Sachiko Kobayashi ,  Suigen Kyoh ,  Shimon Maeda

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in the shape of the pattern data for the modification target point caused by the modification based on the modification guides or a change in electric characteristics of a pattern formed in accordance with the pattern data, selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides, and modifying the modification target point in accordance with the selected modification guide.

Abstract translation: 本发明的一个方式的图形数据生成方法，该方法包括创建至少一个修改指南，以修改包含在图案数据中的修改目标点，基于评估项目评估修改指南，评估项目是 基于修改引导引起的修改目标点的图案数据的形状的改变或根据图案数据形成的图案的电特性的变化，从修改引导件中选择预定的修改指南 修改指南的评估结果的基础，以及根据所选择的修改指南修改修改目标点。

公开(公告)号：US20100067777A1

公开(公告)日：2010-03-18

申请号：US12536900

申请日：2009-08-06

Applicant: Katsuyoshi Kodera ,  Satoshi Tanaka ,  Shimon Maeda ,  Suigen Kyoh ,  Soichi Inoue ,  Ryuji Ogawa

Inventor： Katsuyoshi Kodera ,  Satoshi Tanaka ,  Shimon Maeda ,  Suigen Kyoh ,  Soichi Inoue ,  Ryuji Ogawa

IPC: G06K9/00

CPC classification number: G03F1/44 ,  G03F1/36

Abstract: An evaluation pattern generating method including dividing a peripheral area of an evaluation target pattern into a plurality of meshes; calculating an image intensity of a circuit pattern when the evaluation target pattern is transferred onto a wafer by a lithography process in a case where a mask function value is given to a predetermined mesh; calculating a mask function value of the mesh so that a cost function of the image intensity, in which an optical image characteristic amount that affects a transfer performance of the evaluation target pattern to the wafer is set to the image intensity, satisfies a predetermined reference when evaluating a lithography performance of the evaluation target pattern; and generating an evaluation pattern corresponding to the mask function value.

Abstract translation: 1.一种评价图案生成方法，包括将评价对象图案的周边区域划分为多个网格; 当将掩模函数值赋予预定网格时，通过光刻处理将评估对象图案转印到晶片上时，计算电路图案的图像强度; 计算网格的掩码函数值，使得影响评估对象图案对晶片的转印性能的光学图像特征量被设置为图像强度的图像强度的成本函数满足预定参考，当 评估目标模式的光刻性能评估; 以及生成与所述掩模功能值对应的评估图案。

公开(公告)号：US20060285739A1

公开(公告)日：2006-12-21

申请号：US11448719

申请日：2006-06-08

Applicant: Shimon Maeda

Inventor： Shimon Maeda

IPC: G06K9/00 ,  G06F17/50

CPC classification number: G06K9/6255 ,  G03F1/36 ,  G03F1/68

Abstract: An evaluation pattern generating method includes generating plural types of unit patterns based on a seed pattern group and a unit frame, the seed pattern group including plural types of seed patterns, each of the plural types of unit patterns including a pattern that corresponds to the seed pattern arranged in the unit frame, and generating plural types of evaluation patterns based on the plural types of unit patterns and an arrangement frame having a size that is N times of the unit frame (N is a positive integer), each of the plural types of evaluation patterns including the plural types of evaluation unit patterns arranged in the arrangement frame so that the inside of the arrangement frame is filled with the plural types of the unit patterns.

Abstract translation: 评估模式生成方法包括基于种子图案组和单位框架生成多种类型的单位图案，种子图案组包括多种种子图案，多种类型的单位图案中的每一种包括与种子对应的图案 模式，并且基于多种类型的单位图形生成多种类型的评估模式，并且生成尺寸为单位框架的N倍的排列框（N为正整数），多种类型 包括布置在布置框架中的多种类型的评估单元图案的评估图案，使得布置框架的内部填充有多种类型的单元图案。