公开(公告)号：US06260185B1

公开(公告)日：2001-07-10

申请号：US08930219

申请日：1997-10-20

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： G06G748

CPC分类号： G06F17/505 ,  H03K19/1736 ,  H03K19/1737

摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).

摘要翻译： 用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。 该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤 当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

公开(公告)号：US06313666B1

公开(公告)日：2001-11-06

申请号：US09331780

申请日：1999-06-24

申请人： Shunzo Yamashita ,  Kazuo Yano

发明人： Shunzo Yamashita ,  Kazuo Yano

IPC分类号： H03K19094

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-inut, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass tansistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生电路特性优异的逻辑电路，其面积，延迟时间和功率消耗，从布尔函数创建二进制决策图，并将该图的各个节点映射 成为2-inut，1输出，1控制输入通道晶体管选择器，以合成传输晶体管逻辑电路。 在传输晶体管逻辑电路中，作为NAND或NOR逻辑的传输晶体管选择器，其两个输入中的任何一个不包括固定在逻辑常数“1”或“0”的控制输入，被替换为CMOS门 如果通过替换获得的预定电路特性的值更接近于最佳值（如果所得到的逻辑电路的面积，延迟时间或功耗比原始通路小，则逻辑上等效于通过转换器选择器的NAND或NOR逻辑） 晶体管逻辑电路）。

公开(公告)号：US5923189A

公开(公告)日：1999-07-13

申请号：US633053

申请日：1996-04-16

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/0948

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

摘要翻译： 对于第一和第二通过晶体管电路（PT1，PT2）之间的关系，前级的输出信号被提供给后级的栅极，并且对于第二和第三通过晶体管电路之间的关系 （PT2，PT3），将前级的输出信号提供给后级的源极 - 漏极路径。 第一通过晶体管电路（PT1）在第一输入节点（In1）和第二输入节点（In2）上接收逻辑上彼此独立的第一输入信号和第二输入信号。 该逻辑电路需要较少数量的晶体管，并且能够降低功耗并延迟并完成复杂的逻辑功能。

公开(公告)号：US06609244B2

公开(公告)日：2003-08-19

申请号：US09931879

申请日：2001-08-20

申请人： Naoki Kato ,  Kazuo Yano ,  Hidetoshi Chikata ,  Shunzo Yamashita

发明人： Naoki Kato ,  Kazuo Yano ,  Hidetoshi Chikata ,  Shunzo Yamashita

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： Even if only logic circuits described in HDL are distributed over a network, if the logic synthesis ability is insufficient, the overall design capability cannot be enhanced; e.g., a sufficient performance of a gate level logic circuit cannot be attained, or it takes a long time to complete logic synthesis. Considering design skills for logic synthesis are considered as property, the invention enables distribution of design skills between a plurality of design sites over a network interconnecting computers. Charges for a design skill are set for the rates of improvement to the performance of the logic circuit that was refined by the design skill. Desired circuit performance can be attained in a shorter period by shortening the design phases in which an RTL logic circuit is supplied as input and by logic synthesis thereon, a gate level logic circuit is output.

公开(公告)号：US06400183B2

公开(公告)日：2002-06-04

申请号：US09906264

申请日：2001-07-17

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

IPC分类号： H03K19094

CPC分类号： G06F17/505 ,  H03K19/1737

摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

公开(公告)号：US06259276B1

公开(公告)日：2001-07-10

申请号：US09542620

申请日：2000-04-04

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： H03K19094

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

摘要翻译： 对于第一和第二通过晶体管电路（PT1，PT2）之间的关系，前级的输出信号被提供给后级的栅极，并且对于第二和第三通过晶体管电路之间的关系 （PT2，PT3），将前级的输出信号提供给后级的源极 - 漏极路径。 第一通过晶体管电路（PT1）在第一输入节点（In1）和第二输入节点（In2）上接收逻辑上彼此独立的第一输入信号和第二输入信号。 该逻辑电路需要较少数量的晶体管，并且能够降低功耗并延迟并完成复杂的逻辑功能。

公开(公告)号：US20080208480A1

公开(公告)日：2008-08-28

申请号：US11962316

申请日：2007-12-21

申请人： Hiroyuki KURIYAMA ,  Kazuo Yano ,  Shunzo Yamashita

发明人： Hiroyuki KURIYAMA ,  Kazuo Yano ,  Shunzo Yamashita

IPC分类号： G01D21/00 ,  G06F17/18 ,  G06F19/00

CPC分类号： G01D9/005 ,  G16H50/30 ,  G16H50/50

摘要： For the purpose of effectively supervising a user of the health indexes that cannot always be measured, such as the weight and blood pressure, warning and information are provided based on a prediction of the health indexes. In an information management system, in which a first parameter that is not always measured is predicted from a second always measurable parameter.

摘要翻译： 为了有效地监督用户对体重和血压无法衡量的健康指标，根据健康指标的预测，提供警告和信息。 在信息管理系统中，从第二总是可测量参数预测其中不总是被测量的第一参数。

公开(公告)号：US06696864B2

公开(公告)日：2004-02-24

申请号：US10266773

申请日：2002-10-09

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

IPC分类号： H03K19094

CPC分类号： G06F17/505 ,  H03K19/1737

摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

摘要翻译： 本申请提出了一种新的逻辑电路，包括第一选择器（S1），其中控制输入S由第一输入信号（IN1）控制，输入I1或I0由第二输入信号（IN2）控制，输出 O连接到第一节点（N1），并且第三选择器（S3），其中控制输入S由第一节点（N1）控制，输入I1由第三输入信号（IN3）控制，输入 I0由第一输入信号（IN1）控制，输出端连接到第一输出信号（OUT1）。

公开(公告)号：US06445214B2

公开(公告)日：2002-09-03

申请号：US09956996

申请日：2001-09-21

申请人： Yasuhiko Sasaki ,  Kunihito Rikino ,  Kazuo Yano ,  Shunzo Yamashita

发明人： Yasuhiko Sasaki ,  Kunihito Rikino ,  Kazuo Yano ,  Shunzo Yamashita

IPC分类号： H01L2710

CPC分类号： H01L27/11803 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

公开(公告)号：US06388474B2

公开(公告)日：2002-05-14

申请号：US09860587

申请日：2001-05-21

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： H03K19094

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

摘要翻译： 对于第一和第二通过晶体管电路（PT1，PT2）之间的关系，前级的输出信号被提供给后级的栅极，并且对于第二和第三通过晶体管电路之间的关系 （PT2，PT3），将前级的输出信号提供给后级的源极 - 漏极路径。 第一通过晶体管电路（PT1）在第一输入节点（In1）和第二输入节点（In2）上接收逻辑上彼此独立的第一输入信号和第二输入信号。 该逻辑电路需要较少数量的晶体管，并且能够降低功耗并延迟并完成复杂的逻辑功能。