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    Method for designing semiconductor integrated circuit and automatic designing device
    2.
    发明授权
    Method for designing semiconductor integrated circuit and automatic designing device 失效
    半导体集成电路设计方法及自动设计装置

    公开(公告)号：US06845349B1

    公开(公告)日：2005-01-18

    申请号：US09659735

    申请日：2000-09-11

    申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    IPC分类号： G06F17/50 ,  H03K19/173 ,  G06G7/62

    CPC分类号： H03K19/1737 ,  G06F17/505 ,  H03K19/1736

    摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).

    摘要翻译： 用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。 该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤 当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

    Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit
    3.
    发明授权
    Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit 失效
    包括组合传输晶体管和CMOS电路的逻辑电路和合成逻辑电路的方法

    公开(公告)号：US06820242B2

    公开(公告)日：2004-11-16

    申请号：US10178216

    申请日：2002-06-25

    申请人： Shunzo Yamashita ,  Kazuo Yano

    发明人： Shunzo Yamashita ,  Kazuo Yano

    IPC分类号： G06F1750

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： To produce a logic circuit with excellent characteristics including area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function. Respective nodes are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. A pass transistor selector operating as a NAND or NOR logic with any one of its two inputs, excluding the control input, being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value.

    摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生具有优异特性（包括面积，延迟时间和功耗）的逻辑电路，从布尔函数创建二进制决策图。 各节点映射到2输入1输出1控制输入通道晶体管选择器，以合成传输晶体管逻辑电路。 用作NAND或NOR逻辑的传输晶体管选择器被替换为操作为NAND或NOR逻辑的CMOS栅极，其两个输入中的任一个（不包括控制输入）被固定为逻辑常数“1”或“0” 如果通过替换获得的预定电路特性的值更接近于最佳值，则在逻辑上等效于通过晶体管选择器。

    Logic circuit and its forming method
    4.
    发明授权
    Logic circuit and its forming method 有权

    公开(公告)号：US06486708B2

    公开(公告)日：2002-11-26

    申请号：US10122385

    申请日：2002-04-16

    申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

    发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

    IPC分类号： H03K19094

    CPC分类号： G06F17/505 ,  H03K19/1737

    摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

    Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit
    5.
    发明授权
    Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit 失效
    包括组合传输晶体管和CMOS电路的逻辑电路和合成逻辑电路的方法

    公开(公告)号：US06433588B1

    公开(公告)日：2002-08-13

    申请号：US09940597

    申请日：2001-08-29

    申请人： Shunzo Yamashita ,  Kazuo Yano

    发明人： Shunzo Yamashita ,  Kazuo Yano

    IPC分类号： H03K19094

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

    摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生电路特性优异的逻辑电路，其面积，延迟时间和功率消耗，从布尔函数创建二进制决策图，并将该图的各个节点映射 转换为2输入，1输出，1路控制输入通道晶体管选择器，合成传输晶体管逻辑电路。 在传输晶体管逻辑电路中，作为NAND或NOR逻辑的传输晶体管选择器，其两个输入中的任何一个不包括固定在逻辑常数“1”或“0”的控制输入，被替换为CMOS门 如果通过替换获得的预定电路特性的值更接近于最佳值，逻辑上等效于通过晶体管选择器的NAND或NOR逻辑（如果所得到的逻辑电路的面积，延迟时间或功耗比原始通道小 晶体管逻辑电路）。

    Logic circuit and its forming method
    6.
    发明授权
    Logic circuit and its forming method 失效

    公开(公告)号：US06323690B1

    公开(公告)日：2001-11-27

    申请号：US09610697

    申请日：2000-07-05

    申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

    发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

    IPC分类号： H03K19094

    CPC分类号： G06F17/505 ,  H03K19/1737

    摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

    Method for designing semiconductor integrated circuit and automatic designing device
    7.
    发明授权
    Method for designing semiconductor integrated circuit and automatic designing device 失效
    半导体集成电路设计方法及自动设计装置

    公开(公告)号：US06260185B1

    公开(公告)日：2001-07-10

    申请号：US08930219

    申请日：1997-10-20

    申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    IPC分类号： G06G748

    CPC分类号： G06F17/505 ,  H03K19/1736 ,  H03K19/1737

    摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).

    摘要翻译： 用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。 该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤 当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

    Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit
    8.
    发明授权
    Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit 有权
    包括组合传输晶体管和CMOS电路的逻辑电路和合成逻辑电路的方法

    公开(公告)号：US06313666B1

    公开(公告)日：2001-11-06

    申请号：US09331780

    申请日：1999-06-24

    申请人： Shunzo Yamashita ,  Kazuo Yano

    发明人： Shunzo Yamashita ,  Kazuo Yano

    IPC分类号： H03K19094

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-inut, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass tansistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

    摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生电路特性优异的逻辑电路，其面积，延迟时间和功率消耗，从布尔函数创建二进制决策图，并将该图的各个节点映射 成为2-inut，1输出，1控制输入通道晶体管选择器，以合成传输晶体管逻辑电路。 在传输晶体管逻辑电路中，作为NAND或NOR逻辑的传输晶体管选择器，其两个输入中的任何一个不包括固定在逻辑常数“1”或“0”的控制输入，被替换为CMOS门 如果通过替换获得的预定电路特性的值更接近于最佳值（如果所得到的逻辑电路的面积，延迟时间或功耗比原始通路小，则逻辑上等效于通过转换器选择器的NAND或NOR逻辑） 晶体管逻辑电路）。

    Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections
    9.
    发明授权
    Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections 失效
    半导体集成电路由具有不同相互连接的通过晶体管电路组成

    公开(公告)号：US5923189A

    公开(公告)日：1999-07-13

    申请号：US633053

    申请日：1996-04-16

    申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/0948

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

    摘要翻译： 对于第一和第二通过晶体管电路（PT1，PT2）之间的关系，前级的输出信号被提供给后级的栅极，并且对于第二和第三通过晶体管电路之间的关系 （PT2，PT3），将前级的输出信号提供给后级的源极 - 漏极路径。 第一通过晶体管电路（PT1）在第一输入节点（In1）和第二输入节点（In2）上接收逻辑上彼此独立的第一输入信号和第二输入信号。 该逻辑电路需要较少数量的晶体管，并且能够降低功耗并延迟并完成复杂的逻辑功能。

    Design method of a logic circuit
    10.
    发明授权
    Design method of a logic circuit 失效

    公开(公告)号：US06609244B2

    公开(公告)日：2003-08-19

    申请号：US09931879

    申请日：2001-08-20

    申请人： Naoki Kato ,  Kazuo Yano ,  Hidetoshi Chikata ,  Shunzo Yamashita

    发明人： Naoki Kato ,  Kazuo Yano ,  Hidetoshi Chikata ,  Shunzo Yamashita

    IPC分类号： G06F1750

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： Even if only logic circuits described in HDL are distributed over a network, if the logic synthesis ability is insufficient, the overall design capability cannot be enhanced; e.g., a sufficient performance of a gate level logic circuit cannot be attained, or it takes a long time to complete logic synthesis. Considering design skills for logic synthesis are considered as property, the invention enables distribution of design skills between a plurality of design sites over a network interconnecting computers. Charges for a design skill are set for the rates of improvement to the performance of the logic circuit that was refined by the design skill. Desired circuit performance can be attained in a shorter period by shortening the design phases in which an RTL logic circuit is supplied as input and by logic synthesis thereon, a gate level logic circuit is output.