公开(公告)号：US20080208480A1

公开(公告)日：2008-08-28

申请号：US11962316

申请日：2007-12-21

申请人： Hiroyuki KURIYAMA ,  Kazuo Yano ,  Shunzo Yamashita

发明人： Hiroyuki KURIYAMA ,  Kazuo Yano ,  Shunzo Yamashita

IPC分类号： G01D21/00 ,  G06F17/18 ,  G06F19/00

CPC分类号： G01D9/005 ,  G16H50/30 ,  G16H50/50

摘要： For the purpose of effectively supervising a user of the health indexes that cannot always be measured, such as the weight and blood pressure, warning and information are provided based on a prediction of the health indexes. In an information management system, in which a first parameter that is not always measured is predicted from a second always measurable parameter.

摘要翻译： 为了有效地监督用户对体重和血压无法衡量的健康指标，根据健康指标的预测，提供警告和信息。 在信息管理系统中，从第二总是可测量参数预测其中不总是被测量的第一参数。

公开(公告)号：US07626498B2

公开(公告)日：2009-12-01

申请号：US11208632

申请日：2005-08-23

申请人： Kiyoshi Aiki ,  Hiroyuki Kuriyama ,  Shunzo Yamashita ,  Takanori Shimura

发明人： Kiyoshi Aiki ,  Hiroyuki Kuriyama ,  Shunzo Yamashita ,  Takanori Shimura

IPC分类号： G08B1/08

CPC分类号： H01Q1/273 ,  H01Q9/0485

摘要： To secure a stable radio-communication performance in a sensor node, the sensor node with a radio-communication circuit and a sensor, for transmitting data measured by the sensor through radio-communication, includes a first board BO2 on which an antenna ANT1 connected to the radio-communication circuit is placed, a case CASE1 containing the first board BO2, and a band that is attached to the case CASE1 so as to fix the case CASE1 to the skin. The antenna ANT1 is placed in an upper portion of the case CASE1, which corresponds to a 12 o'clock direction of a wristwatch.

摘要翻译： 为了确保传感器节点中的稳定的无线电通信性能，具有用于通过无线电通信传输由传感器测量的数据的无线电通信电路和传感器的传感器节点包括第一板B02，其上连接有天线ANT1 放置无线电通信电路，包含第一板BO2的壳体CASE1和附接到壳体CASE1的带，以将壳体CASE1固定到皮肤上。 天线ANT1被放置在壳体CASE1的上部，其对应于手表的12点钟方向。

公开(公告)号：US20060229520A1

公开(公告)日：2006-10-12

申请号：US11210740

申请日：2005-08-25

申请人： Shunzo Yamashita ,  Hiroyuki Kuriyama ,  Kiyoshi Aiki ,  Takanori Shimura

发明人： Shunzo Yamashita ,  Hiroyuki Kuriyama ,  Kiyoshi Aiki ,  Takanori Shimura

IPC分类号： A61B5/02

CPC分类号： A61B5/0002 ,  A61B5/02438 ,  A61B5/681 ,  A61B2560/0209

摘要： The precision of measuring biometric information is enhanced while suppressing the consumption of a battery in a sensor node. In a method of measuring the biometric information in a sensor node including a controller for driving a sensor to measure biometric information, the controller supplies power from a battery to an acceleration sensor for detecting the movement of a living body to detect the movement of the living body, the controller determines whether or not measurement by a pulsebeat sensor is possible based on the detected movement of the living body (P330), and shuts off power to the acceleration sensor having a power consumption lower than that of the pulsebeat sensor when the determination results show that measurement is possible, and thereafter supplying power to the pulsebeat sensor having a power consumption larger than that of the acceleration sensor to measure the biometric information (P340).

摘要翻译： 在抑制传感器节点中的电池消耗的同时增强了测量生物信息的精度。 在测量包括用于驱动传感器以测量生物特征信息的控制器的传感器节点中的生物信息的方法中，控制器将电力从电池供给到加速度传感器，用于检测活体的运动以检测生物的移动 控制器基于检测到的活体的移动来确定是否可以通过脉搏波传感器进行测量（P 330），并且在功率消耗低于脉冲波形传感器的功率消耗的加速度传感器时切断电力 确定结果表明测量是可能的，然后向具有大于加速度传感器功率消耗的脉冲波形传感器供电以测量生物特征信息（P 340）。

公开(公告)号：US20070191719A1

公开(公告)日：2007-08-16

申请号：US11723930

申请日：2007-03-22

申请人： Shunzo Yamashita ,  Hiroyuki Kuriyama ,  Kiyoshi Aiki ,  Takanori Shimura

发明人： Shunzo Yamashita ,  Hiroyuki Kuriyama ,  Kiyoshi Aiki ,  Takanori Shimura

IPC分类号： A61B5/02

CPC分类号： A61B5/0002 ,  A61B5/02438 ,  A61B5/681 ,  A61B2560/0209

摘要： The precision of measuring biometric information is enhanced while suppressing the consumption of a battery in a sensor node. In a method of measuring the biometric information in a sensor node including a controller for driving a sensor to measure biometric information, the controller supplies power from a battery to an acceleration sensor for detecting the movement of a living body to detect the movement of the living body, the controller determines whether or not measurement by a pulsebeat sensor is possible based on the detected movement of the living body (P330), and shuts off power to the acceleration sensor having a power consumption lower than that of the pulsebeat sensor when the determination results show that measurement is possible, and thereafter supplying power to the pulsebeat sensor having a power consumption larger than that of the acceleration sensor to measure the biometric information (P340).

摘要翻译： 在抑制传感器节点中的电池消耗的同时增强了测量生物信息的精度。 在测量包括用于驱动传感器以测量生物特征信息的控制器的传感器节点中的生物信息的方法中，控制器将电力从电池供给到加速度传感器，用于检测活体的运动以检测生物的移动 控制器基于检测到的活体的移动来确定是否可以通过脉搏波传感器进行测量（P 330），并且在功率消耗低于脉冲波形传感器的功率消耗的加速度传感器时切断电力 确定结果表明测量是可能的，然后向具有大于加速度传感器功率消耗的脉冲波形传感器供电以测量生物特征信息（P 340）。

公开(公告)号：US06651223B2

公开(公告)日：2003-11-18

申请号：US10287599

申请日：2002-11-05

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.

公开(公告)号：US06505322B2

公开(公告)日：2003-01-07

申请号：US09904661

申请日：2001-07-16

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.

公开(公告)号：US06313665B1

公开(公告)日：2001-11-06

申请号：US09402648

申请日：2000-02-03

申请人： Yasuhiko Sasaki ,  Kunihito Rikino ,  Kazuo Yano ,  Shunzo Yamashita

发明人： Yasuhiko Sasaki ,  Kunihito Rikino ,  Kazuo Yano ,  Shunzo Yamashita

IPC分类号： H01L2710

CPC分类号： H03K19/1737 ,  H01L27/0207 ,  H01L27/11898

摘要： The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

摘要翻译： 传输晶体管逻辑电路单元的I / O端子位置分布在单元中，输出放大器设置在单元的端部，传输晶体管电路沿电位线延伸的方向排列， 信号极性反转电路布置在单元中，并且阱的布置不同于传统CMOS逻辑电路的布置。

公开(公告)号：US6049232A

公开(公告)日：2000-04-11

申请号：US225291

申请日：1999-01-05

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/0948

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

公开(公告)号：US5712792A

公开(公告)日：1998-01-27

申请号：US633486

申请日：1996-04-17

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki ,  Koichi Seki

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki ,  Koichi Seki

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： In order to effectively explore a binary decision diagram for synthesizing a logic circuit, a tentative circuit comprised of AND gates and OR gates is synthesized from a logic function. The number of gates in this circuit to which two input variables are simultaneously associated are counted and used as correlation between the two input variables. A correlation matrix for correlation among all of the input variables is generated. The input variables are sequentially grouped from a set of input variables with strongest correlation in the correlation matrix: These groups are registered into a correlation tree, and an intergroup correlation tree is produced. These groups are sequentially selected from a group with the least correlation, and the intragroup order of the selected group is changed from one to another. A binary decision diagram is explored which satisfies the most appropriate condition in that group (such as the minimum number of nodes, the minimum delay, and the minimum area). The above processes repeated for all groups. Each node of the binary decision diagram thus obtained is substituted by a selector and each selector circuit is substituted by a circuit of a transistor level.

摘要翻译： 为了有效地研究用于合成逻辑电路的二进制判定图，从逻辑功能合成了由与门和或门组成的暂定电路。 两个输入变量同时关联的该电路中的门数被计数并用作两个输入变量之间的相关。 生成所有输入变量之间相关的相关矩阵。 输入变量从相关矩阵中具有最强相关性的一组输入变量顺序分组：将这些组注册到相关树中，并产生一个组间相关树。 从具有最小相关性的组中顺序地选择这些组，并且所选择的组的组内顺序从一个改变为另一组。 探讨了满足该组中最合适条件（如最小节点数，最小延迟和最小面积）的二进制决策图。 上述过程对所有组重复。 由此获得的二进制判定图的每个节点由选择器代替，并且每个选择器电路被晶体管电平的电路代替。

公开(公告)号：US06845349B1

公开(公告)日：2005-01-18

申请号：US09659735

申请日：2000-09-11

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： G06F17/50 ,  H03K19/173 ,  G06G7/62

CPC分类号： H03K19/1737 ,  G06F17/505 ,  H03K19/1736

摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).

摘要翻译： 用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。 该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤 当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。