公开(公告)号：US11769564B2

公开(公告)日：2023-09-26

申请号：US17587633

申请日：2022-01-28

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: G11C27/02 ,  H03K17/687

CPC classification number: G11C27/02 ,  G11C27/024 ,  H03K17/687

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

公开(公告)号：US11264111B2

公开(公告)日：2022-03-01

申请号：US15676757

申请日：2017-08-14

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: G11C27/02 ,  H03K17/687

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

公开(公告)号：US10515708B2

公开(公告)日：2019-12-24

申请号：US15676731

申请日：2017-08-14

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: G11C27/02 ,  H03K17/16

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.

公开(公告)号：US20180348805A1

公开(公告)日：2018-12-06

申请号：US15609644

申请日：2017-05-31

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed ,  Mohamed M. Elkholy

IPC: G05F1/56 ,  G05F1/46 ,  G05F1/595 ,  G05F1/575

Abstract: Embodiments of bias current generator circuits are provided herein for generating stable bias currents. In one embodiment, a bias current generator circuit may include a voltage-to-current generating circuit, an integrate and hold circuit, an amplifier circuit and a plurality of output branches. The voltage-to-current generating circuit may supply a first current to a first node of the bias current generator circuit. The integrate and hold circuit may receive a second current, which is equal to a difference between the first current and a reference current, from the first node and may generate a first voltage in response thereto. The amplifier circuit may receive the first voltage generated by the integrate and hold circuit, and may generate a second voltage in response to the first voltage. The plurality of output branches may receive the second voltage, and may generate a plurality of bias currents in response thereto.