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公开(公告)号：US12153799B2
公开(公告)日：2024-11-26
申请号：US17933183
申请日：2022-09-19
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
IPC: G06F3/06
Abstract: A memory controller for use in a data storage device is provided. The memory controller includes a variable-node circuit and a check-node circuit. The check-node circuit obtains a codeword difference from the variable-node circuit, and calculates a syndrome according to the codeword difference. The variable-node circuit includes a threshold-tracking circuit which is configured to track a threshold used by the variable-node circuit during a low-density parity check (LDPC) decoding process to determine whether the variable-node circuit has entered a trapping status. In response to determining that the variable-node circuit has entered the trapping status during the LDPC decoding process, the variable-node circuit switches a bit-flipping algorithm used by the variable-node circuit during the LDPC decoding process from a first flipping strategy to a post-processing flipping strategy to bring the variable-node circuit out of the trapping status. The first flipping strategy is different from the post-processing flipping strategy.
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公开(公告)号：US10958292B2
公开(公告)日：2021-03-23
申请号：US16691552
申请日：2019-11-21
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
Abstract: An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.
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13.发明申请公开(公告)号：US20200379844A1
公开(公告)日：2020-12-03
申请号：US16423177
申请日：2019-05-28
Applicant: Silicon Motion Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.
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公开(公告)号：US10810120B2
公开(公告)日：2020-10-20
申请号：US16273093
申请日：2019-02-11
Applicant: Silicon Motion Inc.
Inventor： Shiuan-Hao Kuo
Abstract: An encoder of a flash memory controller is provided, which includes a barrel shifter module, an inverse matrix calculating circuit and a calculating circuit. The barrel shifter module processes multiple data blocks to generate multiple partial parity blocks including a first portion, a second portion and a third portion. The inverse matrix calculating circuit performs inverse matrix calculating operations on the first portion to generate a first portion of parity blocks. The calculating circuit performs inverse matrix calculating operations on the second portion and the third portion according to the first portion of the parity blocks, to generate a second portion of the parity blocks and a third portion of the parity blocks. The first portion of the parity blocks, the second portion of the parity blocks, and the third portion of the parity blocks serve as multiple parity blocks generated in response to encoding the data blocks.
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15.发明申请公开(公告)号：US20200153456A1
公开(公告)日：2020-05-14
申请号：US16558146
申请日：2019-09-01
Applicant: Silicon Motion Inc.
Inventor： Shiuan-Hao Kuo
Abstract: The present invention provides an encoding circuit of a flash memory controller, wherein the encoding circuit includes an auxiliary data generating circuit and an encoder. In the operations of the encoding circuit, the auxiliary data generating circuit is configured to receive a plurality of data chunks to generate auxiliary data corresponding to the data chunks. The encoder is configured to encode the data blocks to generate parity codes according to a parity check matrix, and to use the auxiliary data to replace a portion of the parity codes to generate adjusted parity codes, wherein the data chunks and the adjusted parity codes are written into a flash.
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Patent Agency Ranking
公开(公告)号：US12126360B2
公开(公告)日：2024-10-22
申请号：US18207233
申请日：2023-06-08
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
IPC: H03M13/11 , H03K19/173 , H03K19/21
CPC classification number: H03M13/1177 , H03K19/1737 , H03K19/215
Abstract: The invention relates to an apparatus and a method for generating a Low-Density Parity-Check (LDPC) code. The apparatus includes: a LDPC encoder, a look-ahead circuitry and an exclusive-OR (XOR) calculation circuitry. The LDPC encoder is arranged operably to encode a front part of a user data using a 2-stage encoding algorithm with a parity check matrix to generate a first calculation result. The look-ahead circuitry is arranged operably to perform a dot product operation on a rear part of the user data and one of a plurality of feature rows corresponding to the parity check matrix to generate a second calculation result in each iteration. The XOR calculation circuitry is arranged operably to perform an XOR operation on the first calculation result and the second calculation result to generate a front part of the LDPC code.
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公开(公告)号：US11218168B2
公开(公告)日：2022-01-04
申请号：US16849261
申请日：2020-04-15
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A method for generating an LDPC (low-density parity check) code with a required error floor, comprising: using a parity generation circuit to generate an LDPC code; using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information; using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information; using the verification circuit to separately compare each of the estimated error floors with an expected error floor; and when all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code.
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公开(公告)号：US11169878B2
公开(公告)日：2021-11-09
申请号：US17096960
申请日：2020-11-13
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.
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公开(公告)号：US11106531B2
公开(公告)日：2021-08-31
申请号：US16741190
申请日：2020-01-13
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A flash memory controller used to access a flash memory includes a read-only memory, a processor, and an error correction code unit. The read-only memory is used to store a code. The processor executes the code to control access to the flash memory. The error correction code unit includes a control module and a decoder. The control module respectively calculates a first correlation between innate bad-column information which records the location of innate bad columns that become damaged after the read-only memory being manufactured and a plurality of trapping sets of a plurality of preset LDPC (low-density parity check) codes and uses the preset LDPC code which has the lowest first correlation as a selected LDPC code. The decoder decodes read information obtained from the flash memory according to the selected LDPC code.
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公开(公告)号：US20210064466A1
公开(公告)日：2021-03-04
申请号：US17096960
申请日：2020-11-13
Applicant: Silicon Motion, Inc.
Inventor： Shiuan-Hao Kuo
Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.
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