公开(公告)号：US20210090654A1

公开(公告)日：2021-03-25

申请号：US17095661

申请日：2020-11-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Nhan Do ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/063

Abstract: Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.

公开(公告)号：US10943661B2

公开(公告)日：2021-03-09

申请号：US16550253

申请日：2019-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L27/11521 ,  H01L29/788 ,  G06N3/04

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US20200349422A1

公开(公告)日：2020-11-05

申请号：US16449205

申请日：2019-06-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stephen Trinh ,  Thuan Vu ,  Stanley Hong ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/063 ,  G11C16/08

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.

公开(公告)号：US10741568B2

公开(公告)日：2020-08-11

申请号：US16231231

申请日：2018-12-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/04 ,  G06F3/06 ,  H01L27/115 ,  H01L29/788 ,  H01L27/11531 ,  G06N3/08 ,  G11C16/04

Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20200233482A1

公开(公告)日：2020-07-23

申请号：US16354040

申请日：2019-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06F1/3234 ,  G11C16/04 ,  G11C11/54 ,  G06F17/16 ,  G06N3/08

Abstract: Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.

公开(公告)号：US10586598B2

公开(公告)日：2020-03-10

申请号：US16025039

申请日：2018-07-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do

IPC: G11C16/06 ,  G11C16/10 ,  G11C16/28

Abstract: A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.

公开(公告)号：US10580492B2

公开(公告)日：2020-03-03

申请号：US16107282

申请日：2018-08-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  H01L27/11524 ,  G06N3/06 ,  G06N3/063 ,  G11C16/24

Abstract: A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions of the memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

公开(公告)号：US20200035310A1

公开(公告)日：2020-01-30

申请号：US16590798

申请日：2019-10-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C11/54 ,  G11C16/04 ,  G06N3/08 ,  G11C16/30 ,  G11C16/26

Abstract: Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.

公开(公告)号：US10534554B2

公开(公告)日：2020-01-14

申请号：US15784025

申请日：2017-10-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  H01L21/78 ,  H01L27/11521 ,  H01L29/423 ,  H01L23/00

Abstract: Apparatus, and an associated method, for enhancing security and preventing hacking of a flash memory device. The apparatus and method use a random number to offset the read or write address in a memory cell. The random number is generated by determining the leakage current of memory cells. In another embodiment, random data can be written or read in parallel to thwart hackers from determining contents of data being written or read by monitoring sense amplifiers.

公开(公告)号：US10460811B2

公开(公告)日：2019-10-29

申请号：US16387377

申请日：2019-04-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/04

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.