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    Neural Network Classifier Using Array Of Stacked Gate Non-volatile Memory Cells
    11.
    发明申请
    Neural Network Classifier Using Array Of Stacked Gate Non-volatile Memory Cells 审中-公开

    公开(公告)号：US20200242453A1

    公开(公告)日：2020-07-30

    申请号：US16382051

    申请日：2019-04-11

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

    IPC: G06N3/063 ,  H01L27/115

    Abstract: A neural network device with synapses having memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over an entirety of the channel region, and a first gate over the floating gate. First lines each electrically connect together the first gates in one of the memory cell rows, second lines each electrically connect together the source regions in one of the memory cell rows, and third lines each electrically connect together the drain regions in one of the memory cell columns. The synapses are configured to receive a first plurality of inputs as electrical voltages on the first lines or on the second lines, and to provide a first plurality of outputs as electrical currents on the third lines.

    System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
    14.
    发明授权
    System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory 有权

    公开(公告)号：US10600484B2

    公开(公告)日：2020-03-24

    申请号：US15849268

    申请日：2017-12-20

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  H01L29/423 ,  H01L29/788

    Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

    System and method for managing peak power demand and noise in non-volatile memory array
    15.
    发明授权
    System and method for managing peak power demand and noise in non-volatile memory array 有权

    公开(公告)号：US10580491B2

    公开(公告)日：2020-03-03

    申请号：US16015020

    申请日：2018-06-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do ,  Mark Reiten

    IPC: G11C5/08 ,  G11C16/04 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/423

    Abstract: A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.

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