公开(公告)号：US07124274B2

公开(公告)日：2006-10-17

申请号：US10714560

申请日：2003-11-17

申请人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Michael Robert Nonweiler

发明人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Michael Robert Nonweiler

IPC分类号： G06F12/00

CPC分类号： G06F12/145 ,  G06F9/4812 ,  G06F12/1009 ,  G06F12/1027 ,  G06F21/74 ,  G06F2209/481

摘要： An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.

摘要翻译： 一种用于处理数据的装置，所述装置包括：可以多种模式操作的处理器和安全域或非安全域，所述安全域或非安全域包括作为安全域中的模式的至少一个安全模式; 并且至少一个非安全模式是非安全域中的模式。 当处理器以安全模式执行程序时，程序可以访问当处理器以非安全模式运行时无法访问的安全数据。 处理器还包括分别在非安全和安全域中操作的非安全转换表基地址寄存器和安全转换表基地址寄存器，以指示存储非安全或安全域存储器映射数据的存储器区域 定义如何将虚拟地址转换为非安全或安全域中的物理地址。

公开(公告)号：US07117284B2

公开(公告)日：2006-10-03

申请号：US10714562

申请日：2003-11-17

申请人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Jonathan Sean Callan

发明人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Jonathan Sean Callan

IPC分类号： G06F13/24

CPC分类号： G06F9/4812

摘要： A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.

摘要翻译： 数据处理装置可以以多种模式操作，也可以在安全域或非安全域中操作。 当在安全域内以安全模式操作时，程序可以访问当处理器以非安全模式操作时无法访问的安全数据。 提供向量中断控制器以响应于发生除了条件而产生异常处理程序地址。 向量中断控制器是可编程的，参数指定每个异常情况是否应触发安全或非安全域中的异常处理程序，如果在适当的域中发生异常，则使用异常处理程序地址。 向量中断控制器还包括指定域切换异常处理程序地址的参数，以便在处理器不在适当域中时发生异常情况时使用。

公开(公告)号：US07487367B2

公开(公告)日：2009-02-03

申请号：US10714521

申请日：2003-11-17

申请人： Lionel Belnet ,  Nicolas Chaussade ,  Simon Charles Watt ,  Peter Guy Middleton

发明人： Lionel Belnet ,  Nicolas Chaussade ,  Simon Charles Watt ,  Peter Guy Middleton

IPC分类号： H04L9/06 ,  G06F12/00

CPC分类号： G06F12/1491

摘要： The present invention provides a data processing apparatus and method for managing access to a memory within the data processing apparatus. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain, said processor being operable such that when executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode. Further, a memory is provided for storing data required by the processor, and consists of secure memory for storing secure data and non-secure memory for storing non-secure data. The memory further contains a non-secure table and a secure table, the non-secure table being within the non-secure memory and arranged to contain for each of a number of first memory regions an associated descriptor, and the secure table being within the secure memory and arranged to contain for each of a number of second memory regions an associated descriptor. When access to an item of data in the memory is required by the processor, the processor issues a memory access request, and a memory management unit is provided to perform one or more predetermined access control functions to control issuance of the memory access request to the memory. The memory management unit comprises an internal storage unit operable to store descriptors retrieved by the memory management unit from either the non-secure table or the secure table, and in accordance with the present invention the internal storage unit comprises a flag associated with each descriptor stored within the internal storage unit to identify whether that descriptor is from the non-secure table or the secure table. By this approach, when the processor is operating in a non-secure mode, the memory management unit is operable to perform the predetermined access control functions for the memory access request with reference to access control information derived from the descriptors in the internal storage unit retrieved from the non-secure table. In contrast, when the processor is operating in a secure mode, the memory management unit is operable to perform the predetermined access control functions for the memory access request with reference to access control information derived from the descriptors in the internal storage unit retrieved from the secure table. This approach enables different descriptors to be used for the control of accesses to memory in either the secure domain or the non-secure domain, whilst enabling such different descriptors to co-exist within the memory management unit's internal storage unit, thereby avoiding the requirement to flush the contents of such an internal storage unit when the operation of the processor changes from the secure domain to the non-secure domain, or vice versa.

公开(公告)号：US07305534B2

公开(公告)日：2007-12-04

申请号：US10714561

申请日：2003-11-17

申请人： Simon Charles Watt ,  Lionel Belnet ,  David Hennah Mansell ,  Nicolas Chaussade ,  Peter Guy Middleton

发明人： Simon Charles Watt ,  Lionel Belnet ,  David Hennah Mansell ,  Nicolas Chaussade ,  Peter Guy Middleton

IPC分类号： G06F12/00

CPC分类号： G06F12/1491 ,  G06F21/6218 ,  G06F21/71 ,  G06F21/74 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2105 ,  G06F2221/2141 ,  G06F2221/2149

摘要： The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the present invention, the data processing apparatus further comprises partition checking logic coupled to the device bus and operable whenever the memory access request as issued by the device pertains to the non-secure domain, to detect if the memory access request is seeking to access the secure memory and upon such detection to prevent the access specified by that memory request. This approach significantly improves the security of data contained within a secure portion of memory.

摘要翻译： 本发明提供一种用于控制对存储器的访问的数据处理装置和方法。 数据处理装置具有安全域和非安全域，在安全域中，数据处理装置具有对非安全域中不可访问的安全数据的访问。 数据处理装置包括经由设备总线耦合到存储器的设备，并且当设备需要存储器中的数据项时，可以向设备总线发出存储器访问请求，该存储器访问请求涉及安全域或 非安全域。 存储器可操作以存储设备所需的数据，并且包含用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器。 根据本发明，数据处理装置还包括耦合到设备总线的分区检查逻辑，每当由设备发布的存储器访问请求与非安全域相关时，可操作，以检测存储器访问请求是否正在寻找 以访问安全存储器并且在这种检测时防止由该存储器请求指定的访问。 这种方法显着提高了包含在存储器安全部分内的数据的安全性。

公开(公告)号：US20050160210A1

公开(公告)日：2005-07-21

申请号：US10714562

申请日：2003-11-17

申请人： Simon Watt ,  Christopher Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Brochier ,  David Mansell ,  Jonathan Callan

发明人： Simon Watt ,  Christopher Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Brochier ,  David Mansell ,  Jonathan Callan

IPC分类号： G06F9/48 ,  G06F13/24

CPC分类号： G06F9/4812

摘要： There is provided an apparatus for processing data, said apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and a vectored interrupt controller operable to generate an exception handler address for supply to said processor in response to occurrence of an exception condition in accordance with programmable parameters specifying: for each of a plurality of exception conditions, a domain value indicating whether said exception condition should trigger an exception handler in said secure domain or said non-secure domain; for each of said plurality of exception conditions, an exception handler address for use if said exception condition occurs when said processor is operating in that one of said secure domain and said non-secure domain indicated by said domain value; and at least one domain switching exception handler address shared between said plurality of exception conditions for use if said exception condition occurs when said processor is not operating in that one of said secure domain and said non-secure domain indicated by said domain value.

摘要翻译： 提供了一种用于处理数据的装置，所述装置包括：可以多种模式操作的处理器，以及安全域或非安全域，包括：至少一种安全模式是所述安全域中的模式; 并且至少一个非安全模式是所述非安全域中的模式; 其中当所述处理器以安全模式执行程序时，所述程序具有访问当所述处理器以非安全模式操作时不可访问的安全数据; 以及向量中断控制器，其可操作以产生异常处理程序地址，以响应于根据可编程参数发生异常情况而向所述处理器供应，所述可编程参数指定：对于多个异常条件中的每一个，指示所述异常条件是否应当 在所述安全域或所述非安全域中触发异常处理程序; 对于所述多个异常条件中的每一个，如果当所述处理器在由所述域值指示的所述安全域和所述非安全域中的一个中操作时发生所述异常条件，则使用异常处理程序地址; 以及当所述处理器不在由所述域值指示的所述安全域和所述非安全域中的所述安全域中的任何一个时发生所述异常条件时，在所述多个异常条件之间共享的所述多个异常条件之间共享的至少一个域切换异常处理程序地址。

公开(公告)号：US07231476B2

公开(公告)日：2007-06-12

申请号：US10714480

申请日：2003-11-17

申请人： Simon Charles Watt ,  Luc Orion ,  Nicolas Chaussade

发明人： Simon Charles Watt ,  Luc Orion ,  Nicolas Chaussade

IPC分类号： G06F11/30

CPC分类号： G06F9/468

摘要： A processor operable to perform a plurality of functions, the processor comprising: an input port; a storage element operable to receive and to store an input signal input via the input port, the input signal comprising at least one control value; control logic operable to control at least one of the functions of the processor in dependence on the at least one control value; and access logic operable to receive an access control signal and to disable access via the input port to the at least one control value stored in the storage element in dependence upon the access control signal.

摘要翻译： 一种可操作以执行多个功能的处理器，所述处理器包括：输入端口; 存储元件，其可操作以接收并存储经由所述输入端口输入的输入信号，所述输入信号包括至少一个控制值; 控制逻辑可操作以根据所述至少一个控制值来控制所述处理器的功能中的至少一个; 以及访问逻辑，其可操作以接收访问控制信号，并且根据访问控制信号禁止通过输入端口访问存储在存储元件中的至少一个控制值。

公开(公告)号：US08782378B2

公开(公告)日：2014-07-15

申请号：US12923320

申请日：2010-09-14

申请人： Nicolas Chaussade ,  Rémi Teyssier

发明人： Nicolas Chaussade ,  Rémi Teyssier

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30072 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3861

摘要： A data processing apparatus and method are provided. The data processing apparatus is configured to perform data processing operations in response to data processing instructions including a multiple operation instruction, in response to which multiple data processing operations are performed. The data processing apparatus comprises two or more data processing units configured to perform the data processing operations and an instruction arbitration unit configured to perform sub-division of a multiple operation instruction into a plurality of sub-instructions and to perform allocation of the plurality of sub-instructions amongst the two or more data processing units, wherein each sub-instruction is arranged to cause one of the two or more data processing units to perform at least one data processing operation of the multiple data processing operations. The instruction arbitration unit is configured to perform the sub-division and the allocation dynamically in dependence on a current availability of a resource for each of the two or more data processing units, enabling more efficient usage of the resources of each of the data processing units to be made.

摘要翻译： 提供了一种数据处理装置和方法。 数据处理装置被配置为响应于包括多个操作指令的数据处理指令执行数据处理操作，响应于执行多个数据处理操作。 该数据处理装置包括：两个以上的数据处理单元，被配置为执行数据处理操作;以及指令仲裁单元，被配置为执行多个操作指令的分割为多个子指令，并执行多个子指令的分配 - 所述两个或更多个数据处理单元中的指示，其中每个子指令被布置成使所述两个或更多个数据处理单元中的一个执行所述多个数据处理操作的至少一个数据处理操作。 指令仲裁单元被配置为根据两个或多个数据处理单元中的每一个的资源的当前可用性来动态地执行子划分和分配，使得能够更有效地使用每个数据处理单元的资源 被制造。

公开(公告)号：US08769251B2

公开(公告)日：2014-07-01

申请号：US11637948

申请日：2006-12-13

申请人： Philippe Luc ,  Norbert Bernard Eugéne Lataille ,  Florent Begon ,  Nicolas Chaussade

发明人： Philippe Luc ,  Norbert Bernard Eugéne Lataille ,  Florent Begon ,  Nicolas Chaussade

IPC分类号： G06F7/00 ,  G06F15/00

CPC分类号： G06F9/30025 ,  G06F9/30032 ,  G06F9/3824

摘要： A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided for receiving a block of data containing at least one data value, and for converting each data value from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first size, in order to produce re-ordered data. Second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format.

摘要翻译： 提供了一种数据处理装置和方法，用于将数据值从第一端格式转换成第二端格式。 提供了用于接收包含至少一个数据值的数据块，并且将每个数据值从第一个末端格式转换成第二个末端格式的旋转电路。 所述交换电路包括用于对所述数据块执行重新排序操作的第一交换电路，其假定其中包含的所述至少一个数据值具有第一大小，以便产生重新排序的数据。 提供了第二调频电路，其响应于至少一个数据值具有与第一尺寸不同的尺寸的指示，以对已重新排序的数据执行附加的重新排序操作，其中至少考虑到至少 一个数据值，以便将每个数据值转换为第二个末端格式。

公开(公告)号：US07568072B2

公开(公告)日：2009-07-28

申请号：US11513352

申请日：2006-08-31

申请人： Florent Begon ,  Philippe Luc ,  Elodie Charra ,  Nicolas Chaussade

发明人： Florent Begon ,  Philippe Luc ,  Elodie Charra ,  Nicolas Chaussade

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0859 ,  Y02D10/13

摘要： A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information. If it is determined that the data entry should be written to the memory, the eviction logic (1) transfers the information from the eviction buffer to a bus coupled with the memory, (2)transfers data of the first of the plurality of data entries from the cache to a data portion of the eviction buffer, (3) transfers information associated with a second of the plurality of data entries from the cache to the associated portion of the eviction buffer such that the data stored by the data portion of the eviction buffer corresponds to the first of the plurality of data entries and the information stored by the data portion of the eviction buffer corresponds to the second of the plurality of data entries, and (4) transfers the data stored by the data portion of the eviction buffer to the bus. This approach provides a low-power, high performance technique for handling eviction requests.

摘要翻译： 一种方法和数据处理装置，包括具有多个数据条目的高速缓存; 驱逐缓冲器，包括信息部分和数据部分; 以及驱逐逻辑，用于将与所述多个数据条目中的第一数据条目相关联的信息从所述高速缓存传送到所述信息部分，并且参考所述信息来确定所述多个数据条目中的第一条数据条目是否应通过检查被写入存储器 信息。 如果确定数据输入应被写入存储器，驱逐逻辑（1）将信息从驱逐缓冲器传送到与存储器耦合的总线，（2）传送多个数据条目中的第一个的数据 从高速缓存到驱逐缓冲器的数据部分，（3）将与多个数据条目中的第二数据条目相关联的信息从高速缓存传送到驱逐缓冲器的关联部分，使得由驱逐的数据部分存储的数据 缓冲器对应于多个数据条目中的第一个，并且由驱逐缓冲器的数据部分存储的信息对应于多个数据条目中的第二数据条目，并且（4）传送由驱逐缓冲器的数据部分存储的数据 到公共汽车 这种方法提供了一种低功耗，高性能的处理驱逐要求的技术。

公开(公告)号：US20080059722A1

公开(公告)日：2008-03-06

申请号：US11513351

申请日：2006-08-31

申请人： Elodie Charra ,  Nicolas Chaussade ,  Philippe Luc ,  Florent Begon

发明人： Elodie Charra ,  Nicolas Chaussade ,  Philippe Luc ,  Florent Begon

IPC分类号： G06F13/00

CPC分类号： G06F13/4036 ,  G06F9/505 ,  G06F2209/5013

摘要： A data processing apparatus and method which handle data processing requests is disclosed. The data processing apparatus comprises: reception logic operable to receive, for subsequent issue, a request to perform a processing activity; response logic operable to receive an indication of whether the data processing apparatus is currently able, if the request was issued, perform the processing activity in response to that issued request; and optimisation logic operable, in the event that the response logic indicates that the data processing apparatus would be currently unable to perform the processing activities in response to the issued request, to alter pending requests received by the reception logic to improve the performance of the data processing apparatus. Accordingly, the time available whilst waiting for unit to become available can be utilised to analyse the pending requests and to optimize or alter these requests in some way in order to subsequently improve the performance of the data processing apparatus. Hence, once the component is then able to deal with the altered requests, the altered requests will then enable the data processing apparatus to operate more efficiently than had the original requests been used.

摘要翻译： 公开了一种处理数据处理请求的数据处理装置和方法。 数据处理装置包括：接收逻辑，可操作以接收执行处理活动的请求，用于随后的发行; 响应逻辑可操作以接收关于数据处理设备当前是否能够的指示，如果请求被发出，则响应于该发出的请求执行处理活动; 并且优化逻辑可操作，如果所述响应逻辑指示所述数据处理装置当前将不能响应所发出的请求执行所述处理活动，则改变由所述接收逻辑接收的未决请求以提高所述数据的性能 处理装置。 因此，可以利用等待单元变得可用的时间来分析待处理的请求并以某种方式优化或改变这些请求，以便随后改进数据处理装置的性能。 因此，一旦组件然后能够处理改变的请求，则改变的请求将使得数据处理装置能够比原始请求被使用更有效率地进行操作。