公开(公告)号：US20190165186A1

公开(公告)日：2019-05-30

申请号：US16262309

申请日：2019-01-30

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L27/02

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US20180366589A1

公开(公告)日：2018-12-20

申请号：US16110661

申请日：2018-08-23

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/423

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

公开(公告)号：US20160172351A1

公开(公告)日：2016-06-16

申请号：US15052521

申请日：2016-02-24

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.

Abstract translation: 本文公开了一种半导体集成电路器件，其包括具有沿第一方向延伸并沿垂直于第一方向的第二方向布置的多个鳍片的标准单元。 翅片的活动翅片形成有源晶体管的一部分。 翅片的虚拟翅片设置在活动翅片和标准单元的端部之间。

公开(公告)号：US20190164993A1

公开(公告)日：2019-05-30

申请号：US16262183

申请日：2019-01-30

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/118 ,  H01L27/02

Abstract: Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.

公开(公告)号：US20180277537A1

公开(公告)日：2018-09-27

申请号：US15990042

申请日：2018-05-25

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/088 ,  H01L29/66 ,  H03K19/00 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/6681 ,  H03K19/0013

Abstract: Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node. The second n-channel transistor is comprised of m fin transistors having the same gate length and the same gate width where in is greater than n, and has its gate connected to a second input node.

公开(公告)号：US20180190640A1

公开(公告)日：2018-07-05

申请号：US15908356

申请日：2018-02-28

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.

公开(公告)号：US20180130799A1

公开(公告)日：2018-05-10

申请号：US15863107

申请日：2018-01-05

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/088 ,  H01L21/84 ,  H01L27/118 ,  H01L27/12 ,  H01L23/528 ,  H01L27/02 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

公开(公告)号：US20170323887A1

公开(公告)日：2017-11-09

申请号：US15656385

申请日：2017-07-21

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H03K19/00

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/6681 ,  H03K19/0013

Abstract: Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node. The second n-channel transistor is comprised of m fin transistors having the same gate length and the same gate width where m is greater than n, and has its gate connected to a second input node.

公开(公告)号：US20170243888A1

公开(公告)日：2017-08-24

申请号：US15591923

申请日：2017-05-10

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/12 ,  H01L23/66 ,  H01L27/02

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L23/645 ,  H01L23/66 ,  H01L27/0207 ,  H01L27/0629 ,  H01L2223/6677

Abstract: In a circuit block, a plurality of cell rows, each being comprised of a plurality of standard cells arranged in a first direction, are arranged in a second direction perpendicular to the first direction, thereby forming a circuit of SOI transistors. The circuit block includes a plurality of antenna cells, each including an antenna diode provided between a power supply line and a substrate or a well. In at least a part of the circuit block, the antenna cells are arranged at constant intervals in at least one of the first and second directions.

公开(公告)号：US20160172360A1

公开(公告)日：2016-06-16

申请号：US15049680

申请日：2016-02-22

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

Abstract translation: 本文公开了一种半导体集成电路器件，包括具有沿第一方向延伸的翅片的标准单元。 翅片和在垂直于第一方向的第二方向上延伸并设置在翅片上的栅极线构成有源晶体管。 与栅极线并联设置的鳍和伪栅极线构成虚设晶体管。 有源晶体管与虚拟晶体管共享一个节点作为其源极或漏极。