公开(公告)号：US20250158392A1

公开(公告)日：2025-05-15

申请号：US18942029

申请日：2024-11-08

Applicant: Socionext Inc.

Inventor： Isaya SOBUE

IPC: H02H9/04 ,  H01L25/16 ,  H01L27/02

Abstract: A semiconductor device includes: a substrate; first, second, and third substrate power-supply interconnects in the substrate; first and second substrate clamp circuits in the substrate, between the first and second substrate power-supply interconnects, and between the first and third substrate power-supply interconnects, respectively; first and second semiconductor chips on the substrate; first and second chip power-supply interconnects in the first semiconductor chip, electrically-connected to the first substrate power-supply interconnect and to the second substrate power-supply interconnect, respectively; a first circuit in the first semiconductor chip, between the first and second chip power-supply interconnects; third and fourth chip power-supply interconnects in the second semiconductor chip, electrically-connected to the first substrate power-supply interconnect and to the third substrate power-supply interconnect, respectively; and a second circuit in the second semiconductor chip, between the third and fourth chip power-supply interconnects, and a signal from the first circuit is input to the second circuit.

公开(公告)号：US20240421148A1

公开(公告)日：2024-12-19

申请号：US18819621

申请日：2024-08-29

Applicant: Socionext Inc.

Inventor： Isaya SOBUE

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: In an ESD protection circuit using a nanosheet device, a first device structure constituting one of the anode and the cathode is opposed to a second device structure constituting the other in the Y direction, and to a third device structure constituting the other in the X direction. The first device structure includes a pad group of a first conductivity type, and the second and third device structures each include a pad group of a second conductivity type. The length of a range in the X direction in which the pad group of the first device structure is opposed to the pad group of the second device structure in the Y direction is greater than the length of a range in the Y direction in which it is opposed to the pad group of the third device structure in the X direction.

公开(公告)号：US20240072058A1

公开(公告)日：2024-02-29

申请号：US18489440

申请日：2023-10-18

Applicant: Socionext Inc.

Inventor： Isaya SOBUE ,  Hidetoshi TANAKA

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11881

Abstract: In a semiconductor integrated circuit device, an output circuit includes a first transistor connected between VSS and an output terminal. A first power line supplying VSS is formed in a buried interconnect layer, and above the buried interconnect layer, a second power line supplying VSS is formed in an M1 interconnect layer and a third power line connected to the second power line is formed in an M2 interconnect layer. A first output interconnect is formed in the M1 interconnect layer, and a second output interconnect connected to the first output interconnect is formed in the M2 interconnect layer.

公开(公告)号：US20210175172A1

公开(公告)日：2021-06-10

申请号：US17180094

申请日：2021-02-19

Applicant: SOCIONEXT INC.

Inventor： Isaya SOBUE ,  Hidetoshi TANAKA ,  Mai TSUKAMOTO

IPC: H01L23/528 ,  H01L27/02

Abstract: A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.

公开(公告)号：US20200321254A1

公开(公告)日：2020-10-08

申请号：US16905136

申请日：2020-06-18

Applicant: SOCIONEXT INC.

Inventor： Isaya SOBUE

IPC: H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: A layout structure of an output circuit using vertical nanowire (VNW) FETs is provided. The output circuit includes a transistor of a first conductivity type provided between a power supply and an output signal line and configured to receive an output control signal at its gate. The transistor includes a plurality of VNW FETs placed in an array in the X and Y directions, and the plurality of VNW FETs have tops connected to the output signal line, bottoms to which a power supply voltage is supplied, and gates to which the output control signal is supplied.