公开(公告)号：US07903684B2

公开(公告)日：2011-03-08

申请号：US11828286

申请日：2007-07-25

申请人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J3/00 ,  G06F13/00

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US07746798B2

公开(公告)日：2010-06-29

申请号：US10045625

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04L12/18

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US07340558B2

公开(公告)日：2008-03-04

申请号：US10045601

申请日：2001-11-07

申请人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： G06F12/06 ,  G06F13/00 ,  G06F3/00 ,  G11C29/00 ,  G11C7/10 ,  G11C8/00

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US06771192B1

公开(公告)日：2004-08-03

申请号：US10045600

申请日：2001-11-07

申请人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H03M500

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US20080126824A1

公开(公告)日：2008-05-29

申请号：US11828286

申请日：2007-07-25

申请人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： G06F1/08 ,  G06F12/02

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

公开(公告)号：US6144242A

公开(公告)日：2000-11-07

申请号：US148815

申请日：1998-09-04

申请人： Deog-Kyoon Jeong ,  Gyudong Kim ,  David D. Lee

发明人： Deog-Kyoon Jeong ,  Gyudong Kim ,  David D. Lee

IPC分类号： H04B3/04 ,  H04L25/08 ,  H03H11/26

CPC分类号： H04L25/085

摘要： Multiple controllable delays reduce EMI radiated during the transmission of multiple synchronized signals. Each controllable delay introduces a controlled delay into a corresponding signal being transmitted. The controlled delay is such that the combined strength of the multiple signals at peak frequencies is substantially reduced. This results in reduced EMI radiation at those peak frequencies.

摘要翻译： 多个可控延迟降低了传输多个同步信号期间的EMI辐射。 每个可控延迟将受控的延迟引入正在传输的相应信号。 受控的延迟使得峰值频率处的多个信号的组合强度显着降低。 这导致在那些峰值频率下降低了EMI辐射。

公开(公告)号：US08289314B2

公开(公告)日：2012-10-16

申请号：US12569186

申请日：2009-09-29

申请人： Weon-Jun Choe ,  Ah-Reum Kim ,  Kyo-Jin Choo ,  Deog-Kyoon Jeong ,  Do-Hwan Oh ,  Hee-Soo Song

发明人： Weon-Jun Choe ,  Ah-Reum Kim ,  Kyo-Jin Choo ,  Deog-Kyoon Jeong ,  Do-Hwan Oh ,  Hee-Soo Song

IPC分类号： G06F3/038 ,  G11B7/00

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G2310/08 ,  G09G2370/08 ,  H03K7/04

摘要： A method of modulating and demodulating a signal includes modulating data information included in an input data signal provided from an external source and clock information included in an input clock signal provided from the external source into a transmission signal, using (n+1) delay clock signals generated based on the input clock signal, where n is a natural number. The transmission signal is demodulated into an output clock signal including restored clock information and an output data signal including restored data information, using (m+1) delay clock signals generated based on the clock information, where m is a natural number less than n.

摘要翻译： 调制和解调信号的方法包括：使用（n + 1）个延迟时钟将从外部源提供的输入数据信号中包括的数据信息和从外部源提供的输入时钟信号中包括的时钟信息调制成发送信号 基于输入时钟信号生成的信号，其中n是自然数。 使用基于时钟信息生成的（m + 1）个延迟时钟信号，将发送信号解调为包括恢复的时钟信息的输出时钟信号和包括恢复的数据信息的输出数据信号，其中m是小于n的自然数。

公开(公告)号：US20120206176A1

公开(公告)日：2012-08-16

申请号：US13398245

申请日：2012-02-16

申请人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

发明人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

IPC分类号： H03L7/08

CPC分类号： H03L7/0812 ,  H03L7/095 ,  H03L7/101

摘要： A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock.

摘要翻译： 公开了一种粗锁检测器。 课程锁定检测器使用初始锁定范围来确定课程锁定，并且一旦达到课程锁定，则使用修改的锁定范围来确定课程锁定。

公开(公告)号：US20090219739A1

公开(公告)日：2009-09-03

申请号：US12223552

申请日：2006-09-15

申请人： Young-Deok Kim ,  Deog-Kyoon Jeong

发明人： Young-Deok Kim ,  Deog-Kyoon Jeong

IPC分类号： G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04

摘要： A range-matching cell (RMC) includes bit lines (BL); a word line (WL); a match line (ML); search lines (SL); a memory cell (100); a first comparator (110) connected to the memory cell; a second comparator (120) connected to the first comparator, a ground voltage and a predetermined voltage. The comparators conduct a comparing operation in responsive to operator data. Instead of the conventional TCAMs employing 0, 1, and X (don't care) bit, a CAM utilizing the RMC can conduct a comparing operation with less memory by storing the operator data 0 and 1 in advance. Accordingly, memory-use efficiency can be increased.

摘要翻译： 范围匹配单元（RMC）包括位线（BL）; 字线（WL）; 匹配线（ML）; 搜索行（SL）; 存储单元（100）; 连接到所述存储单元的第一比较器（110） 连接到第一比较器的第二比较器（120），接地电压和预定电压。 比较器根据操作员数据进行比较操作。 代替采用0，1和X（无关）位的常规TCAM，使用RMC的CAM可以通过预先存储操作数据0和1来进行具有较少存储器的比较操作。 因此，可以提高记忆使用效率。

公开(公告)号：US07551909B1

公开(公告)日：2009-06-23

申请号：US10651500

申请日：2003-08-29

申请人： Yongsam Moon ,  Young Soo Park ,  Deog-Kyoon Jeong

发明人： Yongsam Moon ,  Young Soo Park ,  Deog-Kyoon Jeong

IPC分类号： H04B1/06

CPC分类号： H03L7/107 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0995

摘要： A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and a folded starved inverter circuit contained within the voltage controlled oscillator wherein the folded starved inverter provides two current paths. The dual current paths allow for simultaneous coarse and fine phase tracking. With this low jitter performance and wide operating range, the quad transceiver may be implemented in 0.18-μm CMOS technology, and shows 10−12 bit error rate up to speeds of 3 Gbps.

摘要翻译： 双电流通道压控振荡器既保留了无缝频率采集和均匀的VCO增益降低，​​又保留了原始工作范围和锁相环特性。 本发明提供了一种四通道收发器，包括一个锁相环电路，该锁相环电路包括用于产生时钟信号的压控振荡器，用于存储要发送的数据的FIFO缓冲器，用于将参考时钟与所产生的时钟进行比较的频率比较器 来自锁相环电路的信号; 以及包含在压控振荡器内的折叠饥饿逆变器电路，其中折叠的饥饿逆变器提供两个电流路径。 双电流路径允许同步粗略和精细的相位跟踪。 凭借这种低抖动性能和广泛的工作范围，四通道收发器可以以0.18微米CMOS技术实现，并显示出10到12位的误码率，达到3 Gbps的速度。