公开(公告)号：US20090219739A1

公开(公告)日：2009-09-03

申请号：US12223552

申请日：2006-09-15

申请人： Young-Deok Kim ,  Deog-Kyoon Jeong

发明人： Young-Deok Kim ,  Deog-Kyoon Jeong

IPC分类号： G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04

摘要： A range-matching cell (RMC) includes bit lines (BL); a word line (WL); a match line (ML); search lines (SL); a memory cell (100); a first comparator (110) connected to the memory cell; a second comparator (120) connected to the first comparator, a ground voltage and a predetermined voltage. The comparators conduct a comparing operation in responsive to operator data. Instead of the conventional TCAMs employing 0, 1, and X (don't care) bit, a CAM utilizing the RMC can conduct a comparing operation with less memory by storing the operator data 0 and 1 in advance. Accordingly, memory-use efficiency can be increased.

摘要翻译： 范围匹配单元（RMC）包括位线（BL）; 字线（WL）; 匹配线（ML）; 搜索行（SL）; 存储单元（100）; 连接到所述存储单元的第一比较器（110） 连接到第一比较器的第二比较器（120），接地电压和预定电压。 比较器根据操作员数据进行比较操作。 代替采用0，1和X（无关）位的常规TCAM，使用RMC的CAM可以通过预先存储操作数据0和1来进行具有较少存储器的比较操作。 因此，可以提高记忆使用效率。

公开(公告)号：US08289314B2

公开(公告)日：2012-10-16

申请号：US12569186

申请日：2009-09-29

申请人： Weon-Jun Choe ,  Ah-Reum Kim ,  Kyo-Jin Choo ,  Deog-Kyoon Jeong ,  Do-Hwan Oh ,  Hee-Soo Song

发明人： Weon-Jun Choe ,  Ah-Reum Kim ,  Kyo-Jin Choo ,  Deog-Kyoon Jeong ,  Do-Hwan Oh ,  Hee-Soo Song

IPC分类号： G06F3/038 ,  G11B7/00

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G2310/08 ,  G09G2370/08 ,  H03K7/04

摘要： A method of modulating and demodulating a signal includes modulating data information included in an input data signal provided from an external source and clock information included in an input clock signal provided from the external source into a transmission signal, using (n+1) delay clock signals generated based on the input clock signal, where n is a natural number. The transmission signal is demodulated into an output clock signal including restored clock information and an output data signal including restored data information, using (m+1) delay clock signals generated based on the clock information, where m is a natural number less than n.

摘要翻译： 调制和解调信号的方法包括：使用（n + 1）个延迟时钟将从外部源提供的输入数据信号中包括的数据信息和从外部源提供的输入时钟信号中包括的时钟信息调制成发送信号 基于输入时钟信号生成的信号，其中n是自然数。 使用基于时钟信息生成的（m + 1）个延迟时钟信号，将发送信号解调为包括恢复的时钟信息的输出时钟信号和包括恢复的数据信息的输出数据信号，其中m是小于n的自然数。

公开(公告)号：US20120206176A1

公开(公告)日：2012-08-16

申请号：US13398245

申请日：2012-02-16

申请人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

发明人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

IPC分类号： H03L7/08

CPC分类号： H03L7/0812 ,  H03L7/095 ,  H03L7/101

摘要： A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock.

摘要翻译： 公开了一种粗锁检测器。 课程锁定检测器使用初始锁定范围来确定课程锁定，并且一旦达到课程锁定，则使用修改的锁定范围来确定课程锁定。

公开(公告)号：US07551909B1

公开(公告)日：2009-06-23

申请号：US10651500

申请日：2003-08-29

申请人： Yongsam Moon ,  Young Soo Park ,  Deog-Kyoon Jeong

发明人： Yongsam Moon ,  Young Soo Park ,  Deog-Kyoon Jeong

IPC分类号： H04B1/06

CPC分类号： H03L7/107 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0995

摘要： A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and a folded starved inverter circuit contained within the voltage controlled oscillator wherein the folded starved inverter provides two current paths. The dual current paths allow for simultaneous coarse and fine phase tracking. With this low jitter performance and wide operating range, the quad transceiver may be implemented in 0.18-μm CMOS technology, and shows 10−12 bit error rate up to speeds of 3 Gbps.

摘要翻译： 双电流通道压控振荡器既保留了无缝频率采集和均匀的VCO增益降低，​​又保留了原始工作范围和锁相环特性。 本发明提供了一种四通道收发器，包括一个锁相环电路，该锁相环电路包括用于产生时钟信号的压控振荡器，用于存储要发送的数据的FIFO缓冲器，用于将参考时钟与所产生的时钟进行比较的频率比较器 来自锁相环电路的信号; 以及包含在压控振荡器内的折叠饥饿逆变器电路，其中折叠的饥饿逆变器提供两个电流路径。 双电流路径允许同步粗略和精细的相位跟踪。 凭借这种低抖动性能和广泛的工作范围，四通道收发器可以以0.18微米CMOS技术实现，并显示出10到12位的误码率，达到3 Gbps的速度。

公开(公告)号：US07113507B2

公开(公告)日：2006-09-26

申请号：US10053461

申请日：2001-11-07

申请人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

发明人： Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

IPC分类号： H04J3/12 ,  H04L12/56

CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

公开(公告)号：US07102446B1

公开(公告)日：2006-09-05

申请号：US11056995

申请日：2005-02-11

申请人： Hyung-Rok Lee ,  Moon-Sang Hwang ,  Sang-Hyun Lee ,  Bong-Joon Lee ,  Deog-Kyoon Jeong

发明人： Hyung-Rok Lee ,  Moon-Sang Hwang ,  Sang-Hyun Lee ,  Bong-Joon Lee ,  Deog-Kyoon Jeong

IPC分类号： H03L7/07 ,  H03L7/087 ,  H04B1/40 ,  H04B1/50

CPC分类号： H03L7/087 ,  H03K23/507 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/10 ,  H03L2207/06 ,  H04L7/0337 ,  Y10S331/02

摘要： A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range. Other aspects are a transceiver (including at least two receiver interfaces and a transmitter interface) implementing a clocking scheme employing no more than three PLLs for clock generation, and a transceiver having a multi-layered receiver interface including digital circuitry and a single clock-generating PLL (an analog PLL for generating a multiphase clock to be shared by all layers of the receiver interface). Each receiver interface layer performs blind oversampling on a different received signal using the multiphase clock and the digital circuitry includes multilayered digital phase lock loop circuitry which receives the oversampled data.

摘要翻译： 用于控制采样时钟或其他时钟的锁相环（PLL）以及数据采样电路，收发器或包括这种PLL的其它装置。 PLL包括多范围VCO，用于控制VCO的至少一个精细控制环路和用于通过改变其频率 - 电压特性来控制VCO的粗略控制环路。 粗调控制回路包括一个频率锁定检测器和电压范围监控逻辑。 通常，当VCO输出时钟频率和参考频率之间的差减小到预定阈值时，频率锁定检测器锁定粗略控制环路的操作，而解锁的粗略控制环路采用电压范围监控逻辑来改变VCO频率 当VCO的精细控制电压离开预定范围时的电压特性。 其他方面是实现采用不超过三个PLL用于时钟产生的时钟方案的收发器（包括至少两个接收器接口和发射器接口），以及具有包括数字电路和单个时钟产生的多层接收器接口的收发器 PLL（用于产生要由接收器接口的所有层共享的多相时钟的模拟PLL）。 每个接收器接口层使用多相时钟在不同的接收信号上执行盲过采样，并且数字电路包括接收过采样数据的多层数字锁相环电路。

公开(公告)号：US06738417B1

公开(公告)日：2004-05-18

申请号：US09393849

申请日：1999-09-09

申请人： Sungjoon Kim ,  Deog-Kyoon Jeong ,  David D. Lee

发明人： Sungjoon Kim ,  Deog-Kyoon Jeong ,  David D. Lee

IPC分类号： H04B138

CPC分类号： H04L5/14 ,  G06F3/14 ,  G09G1/16 ,  G09G2370/045

摘要： A new scheme to transfer bidirectional data streams between a digital display and a computer is disclosed. This bidirectional data transfer can make several I/O devices attach to a display. Existing digital display interfaces are usually unidirectional from a computing to a display. Due to the nature of the existing clocking scheme, backward data transfer from the display side to the computer requires a backward clock. This invention discloses a scheme to send data bidirectionally without sending the additional backward clock. This invention also discloses a scheme to tolerate jitters from the clock source. With this approach, this new interface can make a digital display an I/O concentrator.

摘要翻译： 公开了一种在数字显示器和计算机之间传输双向数据流的新方案。 这种双向数据传输可以使多个I / O设备连接到显示器。 现有的数字显示接口通常是从计算到显示的单向的。 由于现有的时钟方案的性质，从显示侧到计算机的反向数据传输需要一个反向时钟。 本发明公开了一种双向发送数据的方案，而不发送额外的反向时钟。 本发明还公开了一种允许来自时钟源的抖动的方案。 通过这种方式，这个新界面可以使数字显示器成为一个I / O集中器。

公开(公告)号：US06600771B1

公开(公告)日：2003-07-29

申请号：US09234777

申请日：1999-01-20

申请人： Yongsam Moon ,  Deog-Kyoon Jeong ,  Gyudong Kim

发明人： Yongsam Moon ,  Deog-Kyoon Jeong ,  Gyudong Kim

IPC分类号： H04B169

CPC分类号： H04B1/707 ,  G06F1/04 ,  H04B15/00 ,  H04B15/04 ,  H04B2215/064

摘要： A new spread spectrum phase modulation (SSPM) technique is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.

摘要翻译： 新的扩频相位调制（SSPM）技术适用于数据和时钟信号。 SSPM技术比直接序列扩频（DSSS）技术更适合板级设计。 此外，SSPM可以与受控边缘速率信令组合以优于DSSS。

公开(公告)号：US06313688B1

公开(公告)日：2001-11-06

申请号：US09709315

申请日：2000-11-13

申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

IPC分类号： G06F744

CPC分类号： H04B1/40 ,  H03D7/1441 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/403

摘要： A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.

摘要翻译： 根据本发明的混合器结构及其使用方法包括多相混合器。 VCO包括多个差分延迟单元，以输出多个多相时钟信号。 多相混频器可以包括负载电路，开关电路，降噪电路和输入电路。 开关电路被耦合以接收多个多相时钟信号，并且包括分别耦合到负载电路的第一开关阵列和第二开关阵列。 耦合到开关电路的降噪电路可以包括响应偏置电压的晶体管。 输入电路包括接收输入信号的晶体管。 第一开关阵列包括耦合在第一输出端子和第二节点之间的第一多个开关，并且第二开关阵列包括耦合在第二输出端子和第二节点之间的第二多个开关。 优选地，多个开关中的每一个包括两对串联连接的晶体管，其中串联连接的晶体管并联耦合以为两个输入端口中的每一个提供对称电连接。 混频器和使用它的方法可以是接收RF输入信号的单或双平衡混频器。

公开(公告)号：US06271816B1

公开(公告)日：2001-08-07

申请号：US09148583

申请日：1998-09-04

申请人： Deog-Kyoon Jeong ,  Gyudong Kim

发明人： Deog-Kyoon Jeong ,  Gyudong Kim

IPC分类号： G09G336

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2330/021 ,  G09G2330/023

摘要： Switches and capacitors are efficiently used to passively change the voltage level on column electrodes without active driving by the column driver circuit. This significantly reduces the power needed by the column driver circuit to drive voltages of alternating polarity onto the column electrodes. In this way, significant power is saved in both the pixel inversion and the row inversion schemes. The average power savings of various of the embodiments exceeds 50% compared with a simple conventional implementation of a column driver circuit. Another aspect similarly reduces the power used by the column driver circuit in the back plane switching scheme.

摘要翻译： 开关和电容器被有效地用于被动地改变列电极上的电压电平，而无需由列驱动电路进行有源驱动。 这显着地降低了列驱动电路所需的功率，以驱动交替极性的电压到列电极上。 以这种方式，在像素反转和行反转方案中节省了显着的功率。 与列驱动电路的简单常规实施方式相比，各种实施例的平均功率节省超过了50％。 另一方面类似地减少了在背面切换方案中列驱动电路所使用的功率。