公开(公告)号：US20190139828A1

公开(公告)日：2019-05-09

申请号：US16199498

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3213

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

公开(公告)号：US09803274B2

公开(公告)日：2017-10-31

申请号：US14080561

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei Bih ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Hsien-Chieh Hsiao ,  Chang-Sheng Lee ,  Wei-Chen Liao ,  Wei Zhang

IPC: C23C14/35 ,  C23C14/34 ,  H01J37/34 ,  H01J37/32 ,  C23C14/56

CPC classification number: C23C14/34 ,  C23C14/564 ,  H01J37/32467 ,  H01J37/32477 ,  H01J37/34 ,  H01J37/3411 ,  H01J37/3426 ,  H01J37/3447

Abstract: A physical vapor deposition (PVD) chamber, a process kit of a PVD chamber and a method of fabricating a process kit of a PVD chamber are provided. In various embodiments, the PVD chamber includes a sputtering target, a power supply, a process kit, and a substrate support. The sputtering target has a sputtering surface that is in contact with a process region. The power supply is electrically connected to the sputtering target. The process kit has an inner surface at least partially enclosing the process region, and a liner layer disposed on the inner surface. The substrate support has a substrate receiving surface, wherein the liner layer disposed on the inner surface of the process kit has a surface roughness (Rz), and the surface roughness (Rz) is substantially in a range of 50-200 μm.

公开(公告)号：US09685441B2

公开(公告)日：2017-06-20

申请号：US15376353

申请日：2016-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Wei Zhang

IPC: H01L29/51 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

Abstract: The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, a barrier layer and a silicide layer. The substrate has a trench. The gate dielectric multi-layer overlies the trench, in which the gate dielectric multi-layer includes a high-k capping layer with a fluorine concentration substantially in a range from 1 at % to 10 at %. The etch stop layer is disposed on the gate dielectric multi-layer. The work function metallic layer is disposed on the etch stop layer. The barrier layer is disposed on the work function metallic layer. The silicide layer is disposed on the barrier layer.