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    Threshold Voltage Tuning for Fin-Based Integrated Circuit Device
    1.
    发明申请
    Threshold Voltage Tuning for Fin-Based Integrated Circuit Device 有权

    公开(公告)号：US20220254687A1

    公开(公告)日：2022-08-11

    申请号：US17734327

    申请日：2022-05-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

    IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/088

    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

    Threshold Voltage Tuning for Fin-Based Integrated Circuit Device
    3.
    发明申请
    Threshold Voltage Tuning for Fin-Based Integrated Circuit Device 审中-公开

    公开(公告)号：US20190139828A1

    公开(公告)日：2019-05-09

    申请号：US16199498

    申请日：2018-11-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3213

    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

    Apparatus for electro-chemical plating
    4.
    发明授权
    Apparatus for electro-chemical plating 有权

    公开(公告)号：US11427924B1

    公开(公告)日：2022-08-30

    申请号：US17232161

    申请日：2021-04-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuo-Lung Hou ,  Ming-Hsien Lin ,  Tsung-Cheng Wu

    IPC: C25D21/12 ,  C25D7/12 ,  C25D5/54 ,  C25D21/00 ,  C25D17/00

    Abstract: An electrochemical plating apparatus for depositing a conductive material on a wafer includes a cell chamber. The plating solution is provided from a bottom of the cell chamber into the cell chamber. A plurality of openings passes through a sidewall of the cell chamber. A flow regulator is arranged with each of the plurality of openings configured to regulate an overflow amount of the plating solution flowing out through the each of the plurality of openings. The electrochemical plating apparatus further comprises a controller to control the flow regulator such that overflow amounts of the plating solution flowing out through the plurality of openings are substantially equal to each other.

    Threshold voltage tuning for fin-based integrated circuit device
    5.
    发明授权
    Threshold voltage tuning for fin-based integrated circuit device 有权

    公开(公告)号：US11322410B2

    公开(公告)日：2022-05-03

    申请号：US16199498

    申请日：2018-11-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

    IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/088 ,  H01L27/12

    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

    Atomic layer deposition based process for contact barrier layer
    6.
    发明授权
    Atomic layer deposition based process for contact barrier layer 有权

    公开(公告)号：US10170322B1

    公开(公告)日：2019-01-01

    申请号：US15815059

    申请日：2017-11-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Yu-Lin Liu ,  Ming-Hsien Lin ,  Tzo-Hung Luo

    IPC: H01L21/285 ,  H01L23/532 ,  H01L21/768

    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.

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