公开(公告)号：US20150067426A1

公开(公告)日：2015-03-05

申请号：US14473380

申请日：2014-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lewis Nardini ,  Sumant Kale ,  Alan Hales

IPC: G01R31/3177

CPC classification number: G01R31/318547 ,  G01R31/318385 ,  G01R31/318575

Abstract: Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.

Abstract translation: 用于测试集成电路的装置和方法。 集成电路包括要测试的电路，扫描链逻辑和测试适配器。 扫描链逻辑被配置为将测试数据传送到电路并从其测试结果。 测试适配器被配置为从自动测试控制系统接收的分组中提取测试数据，并将测试数据传送到扫描链逻辑。 测试适配器还被配置为从扫描链逻辑接收测试结果，并将测试结果打包以传输到自动测试控制系统。

公开(公告)号：US20130021055A1

公开(公告)日：2013-01-24

申请号：US13629854

申请日：2012-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Alan Hales

IPC: G01R31/26

CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

公开(公告)号：US10120025B2

公开(公告)日：2018-11-06

申请号：US15795943

申请日：2017-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Alan Hales

IPC: G01R31/3185 ,  G01R31/3177

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

公开(公告)号：US09702935B2

公开(公告)日：2017-07-11

申请号：US14473380

申请日：2014-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lewis Nardini ,  Sumant Kale ,  Alan Hales

IPC: G06F11/00 ,  G01R31/3185 ,  G01R31/3183

CPC classification number: G01R31/318547 ,  G01R31/318385 ,  G01R31/318575

Abstract: Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.

公开(公告)号：US09322879B2

公开(公告)日：2016-04-26

申请号：US14792384

申请日：2015-07-06

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Alan Hales

IPC: H01L23/48 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/319 ,  G01R1/073

CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract translation: 位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。 来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。 还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。 信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3）都可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出 芯片/ IC输出。 除功能测试外，还可以对芯片和IC进行扫描测试。

公开(公告)号：US08872178B2

公开(公告)日：2014-10-28

申请号：US14187691

申请日：2014-02-24

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Alan Hales

IPC: H01L23/58 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/319 ,  G01R1/073

CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract translation: 位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。 来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。 还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。 信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出 芯片/ IC输出。 除功能测试外，还可以对芯片和IC进行扫描测试。

公开(公告)号：US20140167792A1

公开(公告)日：2014-06-19

申请号：US14187691

申请日：2014-02-24

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Alan Hales

IPC: G01R31/319

CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract translation: 位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。 来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。 还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。 信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3）都可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出 芯片/ IC输出。 除功能测试外，还可以对芯片和IC进行扫描测试。