公开(公告)号：US08987748B2

公开(公告)日：2015-03-24

申请号：US13719511

申请日：2012-12-19

Applicant: Texas Instruments Incorporated

Inventor： Himadri Sekhar Pal ,  Youn Sung Choi ,  Amitabh Jain

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer prior to etching the source drain regions for epitaxial replacement. The anti-punch-through layer is disposed between stressor tips of the epitaxial source and drain regions, and does not substantially extend into the epitaxial source and drain regions.

Abstract translation: 包含具有外延源极和漏极区域的MOS晶体管的集成电路可以在蚀刻用于外延替换的源极漏极区域之前注入逆向抗穿通层来形成。 防穿透层设置在外延源极和漏极区域的应力尖端之间，并且基本上不延伸到外延源极和漏极区域中。

公开(公告)号：US08865549B2

公开(公告)日：2014-10-21

申请号：US13707865

申请日：2012-12-07

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong Lim ,  Stanley Seungchul Song ,  Amitabh Jain

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

Abstract translation: 一种金属氧化物半导体晶体管（MOS）及其制造方法，其中有效沟道长度相对于栅电极的宽度增加。 在结构的表面上形成覆盖虚拟栅极电介质材料的虚拟栅电极，在虚拟栅极结构的侧壁上具有自对准的源极/漏极区域和电介质间隔物。 虚拟栅极电介质位于侧壁间隔物的正下方。 在去除虚拟栅极电极和下面的虚拟栅极电介质材料之后，包括从间隔物下方进行硅蚀刻以在下面的衬底中形成凹陷。 由于相对于凹部底部的蚀刻的晶体取向，该蚀刻在底切侧上是自限制的。 然后将栅极电介质和栅电极材料沉积到剩余的空隙中，例如形成高k金属栅极MOS晶体管。

公开(公告)号：US20130095630A1

公开(公告)日：2013-04-18

申请号：US13654161

申请日：2012-10-17

Applicant: Texas Instruments Incorporated

Inventor： Ebenezer Eshun ,  Himadri Sekhar Pal ,  Amitabh Jain

IPC: H01L21/266

CPC classification number: H01L21/823412 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon implant and a zero-degree carbon implant that is substantially perpendicular to a top surface of the integrated circuit. The split carbon co-implant is done at the LDD and halo implant steps.

Abstract translation: 可以使用裂缝碳共注入形成包含MOS晶体管的集成电路。 分裂碳共植入物包括角度碳植入物和零度碳植入物，其基本上垂直于集成电路的顶表面。 分裂碳共注入在LDD和晕轮植入步骤完成。