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    Integrated circuit with debugger and arbitration interface
    14.
    发明授权
    Integrated circuit with debugger and arbitration interface 有权

    公开(公告)号：US12204393B2

    公开(公告)日：2025-01-21

    申请号：US18505037

    申请日：2023-11-08

    Applicant: Texas Instruments Incorporated

    Inventor： Jose Luis Flores ,  Gary Augustine Cooper ,  Amritpal Singh Mundra ,  Anthony Lell ,  Jason Lynn Peck

    IPC: G06F11/00 ,  G06F1/3203 ,  G06F11/36

    Abstract: Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

    SECURE MESSAGE ROUTING
    16.
    发明申请
    SECURE MESSAGE ROUTING 有权

    公开(公告)号：US20210374286A1

    公开(公告)日：2021-12-02

    申请号：US17402693

    申请日：2021-08-16

    Applicant: Texas Instruments Incorporated

    Inventor： Amritpal Singh Mundra ,  Eric Lasmana

    IPC: G06F21/72 ,  G06F15/78 ,  G06F21/74 ,  G06F9/54

    Abstract: In described examples, a method of routing messages in a system on a chip (SoC) includes a secure message router receiving a message including a content, an identifier of the message's sending (origin) functional block and/or of a receiving (destination) functional block, a message secure value, a promote value, and a demote value. A context corresponding to the identifier is retrieved from a memory. The context includes an allow promote value and an allow demote value. The message secure value is increased if the promote value requests the increase and matches the allow promote value. The message secure value is decreased if the demote value requests the decrease and matches the allow demote value. Cleartext corresponding to the content is made accessible by the destination if the context secure value matches the message secure value. The message is then outputted from the secure message router to the destination.

    FLEXIBLE HYBRID FIREWALL ARCHITECTURE
    18.
    发明申请
    FLEXIBLE HYBRID FIREWALL ARCHITECTURE 审中-公开

    公开(公告)号：US20200304464A1

    公开(公告)日：2020-09-24

    申请号：US16786734

    申请日：2020-02-10

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Amritpal Singh Mundra ,  Brian J. Karguth ,  Timothy Anderson ,  Kai Chirca ,  Charles Fuoco

    IPC: H04L29/06

    Abstract: A flexible hybrid firewall architecture is disclosed. A system implementing such an architecture includes an access control register, a memory having at least a region to which access is controllable by the access control register, the access control register including first field that contains a privilege identifier (ID) and a plurality of additional fields, each additional field containing control bits corresponding to a respective one of a plurality of permission levels, and control circuitry that, in response to receiving a transaction containing a transaction privilege ID, a security indicator, and a privilege indicator, controls access to the region when the transaction privilege ID matches the privilege ID contained in the first field by using the control bits of a field of the additional fields that corresponds to a security level indicated by the security indicator and a privilege level indicated by the privilege indicator of the transaction.

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