公开(公告)号：US20220223581A1

公开(公告)日：2022-07-14

申请号：US17321492

申请日：2021-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krishna Praveen Mysore Rajagopal ,  James Paul DiSarro ,  Ann Margaret Concannon ,  Rajkumar Sankaralingam

IPC: H01L27/02 ,  H02H9/04

Abstract: An ESD protection system including structure to operate an IC during nominal conditions, to protect the IC during an ESD event, and to allow the IC to operate during slow rising input node voltages that exceed nominal conditions.

公开(公告)号：US20200235571A1

公开(公告)日：2020-07-23

申请号：US16558867

申请日：2019-09-03

Applicant: Texas Instruments Incorporated

Inventor： Ann Margaret Concannon ,  Vishwanath Joshi ,  Antonio Gallerano ,  Zhao Gao ,  Yanqing Li

IPC: H02H9/04 ,  H03H11/02

Abstract: A protection circuit for a signal processor, a method of operating the protection circuit, and a method of forming the protection circuit. In one example, the protection circuit is couplable to a signal port and a first power bus for the signal processor. The protection circuit includes a first diode string couplable across the signal port and the first power bus. The first diode string includes a first diode and a second diode coupled in series in a same polarity sense. The protection circuit also includes a third diode coupled in parallel with one of the first diode and the second diode in an opposite polarity sense.

公开(公告)号：US10163888B2

公开(公告)日：2018-12-25

申请号：US15359833

申请日：2016-11-23

Applicant: Texas Instruments Incorporated

Inventor： Antonio Gallerano ,  Ann Margaret Concannon ,  Krishna Praveen Mysore Rajagopal

IPC: H01L27/02 ,  H01L29/747 ,  H01L29/06 ,  H01L29/74

Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.

公开(公告)号：US09633990B2

公开(公告)日：2017-04-25

申请号：US15188235

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Aravind C. Appaswamy ,  Ann Margaret Concannon

IPC: H01L21/8238 ,  H01L21/8222 ,  H01L23/62 ,  H01L27/02 ,  H01L27/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/747

CPC classification number: H01L27/0259 ,  H01L21/265 ,  H01L21/8222 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/66386 ,  H01L29/735 ,  H01L29/747

Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.

公开(公告)号：US10763251B2

公开(公告)日：2020-09-01

申请号：US15715988

申请日：2017-09-26

Applicant: Texas Instruments Incorporated

Inventor： Krishna Praveen Mysore Rajagopal ,  James P Di Sarro ,  Mariano Dissegna ,  Lihui Wang ,  Ann Margaret Concannon

IPC: H02H9/04 ,  H01L27/02 ,  H02H3/20 ,  H01L29/808

Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.

公开(公告)号：US20190096874A1

公开(公告)日：2019-03-28

申请号：US15715988

申请日：2017-09-26

Applicant: Texas Instruments Incorporated

Inventor： Krishna Praveen Mysore Rajagopal ,  James P. Di Sarro ,  Mariano Dissegna ,  Lihui Wang ,  Ann Margaret Concannon

IPC: H01L27/02 ,  H02H3/20

Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.

公开(公告)号：US20180152019A1

公开(公告)日：2018-05-31

申请号：US15361736

申请日：2016-11-28

Applicant: Texas Instruments Incorporated

Inventor： Krishna Praveen Mysore Rajagopal ,  Ann Margaret Concannon ,  Vishwanath Joshi ,  Aravind Chennimalai Appaswamy ,  Mariano Dissegna

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255

Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.

公开(公告)号：US20160300831A1

公开(公告)日：2016-10-13

申请号：US15188235

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Aravind C. Appaswamy ,  Ann Margaret Concannon

IPC: H01L27/02 ,  H01L29/66 ,  H01L21/265 ,  H01L29/747

CPC classification number: H01L27/0259 ,  H01L21/265 ,  H01L21/8222 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/66386 ,  H01L29/735 ,  H01L29/747

Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.

公开(公告)号：US20150187752A1

公开(公告)日：2015-07-02

申请号：US14578747

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Aravind C. Appaswamy ,  Ann Margaret Concannon

IPC: H01L27/02 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L27/0259 ,  H01L21/265 ,  H01L21/8222 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/66386 ,  H01L29/735 ,  H01L29/747

Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.

Abstract translation: 具有双向ESD晶体管的集成电路和方法。 基极扩散分离发射极扩散和集电极扩散。 硅化物从基极扩散，发射极 - 基极结，集电极 - 基极结以及发射极扩散和集电极扩散的相等部分封闭。