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公开(公告)号：US12111778B2
公开(公告)日：2024-10-08
申请号：US17558252
申请日：2021-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Mody , Niraj Nandan , Hetul Sanghvi , Brian Chae , Rajasekhar Reddy Allu , Jason A. T. Jones , Anthony Lell , Anish Reghunath
CPC classification number: G06F13/1668 , G06F13/28 , G06T1/20 , H04N5/765
Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.
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公开(公告)号：US11863713B2
公开(公告)日：2024-01-02
申请号：US16669138
申请日：2019-10-30
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Brian Chae , Mihir Mody , Rajasekhar Reddy Allu
CPC classification number: H04N17/004 , H04N5/144 , H04N7/183
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for image frame freeze detection. An example hardware accelerator includes a core logic circuit to generate second image data based on first image data associated with a first image frame, the second image data corresponding to at least one of processed image data, transformed image data, or one or more image data statistics, a load/store engine (LSE) coupled to the core logic circuit, the LSE to determine a first CRC value based on the second image data obtained from the core logic circuit, and a first interface coupled to a second interface, the second interface coupled to memory, the first interface to transmit the first CRC value obtained from the memory to a host device.
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13.发明公开公开(公告)号：US20230229610A1
公开(公告)日：2023-07-20
申请号：US18190242
申请日：2023-03-27
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Rajasekhar Reddy Allu , Brian Chae , Mihir Mody
CPC classification number: G06F13/28 , G06F9/4881 , G06F13/1673 , G06F13/4027 , G06F2213/0038
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.
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公开(公告)号：US11615043B2
公开(公告)日：2023-03-28
申请号：US17139970
申请日：2020-12-31
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Rajasekhar Reddy Allu , Brian Chae , Mihir Mody
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.
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公开(公告)号：US11436171B2
公开(公告)日：2022-09-06
申请号：US16704820
申请日：2019-12-05
Applicant: Texas Instruments Incorporated
Inventor： Anish Reghunath , Brian Chae , Jay Scott Salinger , Chunheng Luo
IPC: G06F12/02 , G06F13/28 , G06F12/1081 , G06F3/14
Abstract: A system includes a display subsystem. The display subsystem includes a shared buffer having allocated portions, each allocated to one of a plurality of display threads, each display thread associated with a display peripheral. The display subsystem also includes a direct memory access (DMA) engine configured to receive a request from a main processor to deallocate an amount of space from a first allocated portion associated with a first display thread. In response to receiving the request, the DMA engine deallocates the amount of space from the first allocated portion and shifts the allocated portions of at least some of other display threads to maintain contiguity of the allocated portions and concatenate free space at an end of the shared buffer.
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Patent Agency Ranking
公开(公告)号：US20240427716A1
公开(公告)日：2024-12-26
申请号：US18816201
申请日：2024-08-27
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Rajasekhar Reddy Allu , Brian Chae , Mihir Mody
Abstract: Systems and methods enable data aggregation and pattern adaptation in hardware acceleration subsystems. In an example, a system, which may be a hardware thread scheduling system, includes schedulers, each associated with a pattern adapter; hardware accelerators respectively coupled to the schedulers; load store engines respectively associated with the hardware accelerators; a memory coupled to the load store engines; and a direct memory access (DMA) circuit coupled to the memory. Each pattern adapter is able to convert data from one format to another, and each load store engine is able to aggregate data elements to form larger data elements to improve overall processing efficiency.
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公开(公告)号：US11947477B2
公开(公告)日：2024-04-02
申请号：US17887906
申请日：2022-08-15
Applicant: Texas Instruments Incorporated
Inventor： Anish Reghunath , Brian Chae , Jay Scott Salinger , Chunheng Luo
IPC: G06F12/02 , G06F3/14 , G06F12/1081 , G06F13/28
CPC classification number: G06F13/28 , G06F3/14 , G06F12/1081
Abstract: A system includes a display subsystem. The display subsystem includes a shared buffer having allocated portions, each allocated to one of a plurality of display threads, each display thread associated with a display peripheral. The display subsystem also includes a direct memory access (DMA) engine configured to receive a request from a main processor to deallocate an amount of space from a first allocated portion associated with a first display thread. In response to receiving the request, the DMA engine deallocates the amount of space from the first allocated portion and shifts the allocated portions of at least some of other display threads to maintain contiguity of the allocated portions and concatenate free space at an end of the shared buffer.
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公开(公告)号：US20240089425A1
公开(公告)日：2024-03-14
申请号：US18510884
申请日：2023-11-16
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Brian Chae , Mihir Mody , Rajasekhar Reddy Allu
CPC classification number: H04N17/004 , H04N5/144 , H04N7/183
Abstract: Devices, systems, and methods detect an image frame freeze condition. An example device includes a core logic circuit configured to generate statistics for received image data associated with an image frame, perform a census transform on pixel values of the image data to generate census transformed data, arrange the census transformed data into a binary string having a binary value, and generate transformed image data by replacing a select pixel value of the pixel values of the image data with a decimal value corresponding to the binary value; a load/store engine (LSE) coupled to the core logic circuit, the LSE configured to determine a cyclic redundancy check (CRC) value based on at least one of the image data, the transformed image data, and at least one statistic of the statistics; and an interface configured to transmit the CRC value to a host device.
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公开(公告)号：US20210209041A1
公开(公告)日：2021-07-08
申请号：US17139970
申请日：2020-12-31
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Rajasekhar Reddy Allu , Brian Chae , Mihir Mody
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.
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公开(公告)号：US10534736B1
公开(公告)日：2020-01-14
申请号：US16237388
申请日：2018-12-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anish Reghunath , Brian Chae , Jay Scott Salinger , Chunheng Luo
IPC: G06F12/02 , G06F13/28 , G06F12/1081 , G06F3/14
Abstract: A system includes a display subsystem. The display subsystem includes a shared buffer having allocated portions, each allocated to one of a plurality of display threads, each display thread associated with a display peripheral. The display subsystem also includes a direct memory access (DMA) engine configured to receive a request from a main processor to deallocate an amount of space from a first allocated portion associated with a first display thread. In response to receiving the request, the DMA engine deallocates the amount of space from the first allocated portion and shifts the allocated portions of at least some of other display threads to maintain contiguity of the allocated portions and concatenate free space at an end of the shared buffer.
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