公开(公告)号：US20240364276A1

公开(公告)日：2024-10-31

申请号：US18648037

申请日：2024-04-26

Applicant: Texas Instruments Incorporated

Inventor： Chandrasekhar Sriram ,  Sarma Sundareswara Gunturi ,  Jawaharlal Tangudu ,  Harshit Moondra ,  Harsh Garg ,  Sanjay Pennam

IPC: H03F1/32 ,  H03F3/24

CPC classification number: H03F1/3241 ,  H03F3/245 ,  H03F2200/451

Abstract: Methods, apparatus, systems, and articles of manufacture are described for dynamic digital pre-distortion correction. An example system includes programmable circuitry operable to execute computer readable instructions to at least: generate signal statistics based on an input signal; group the signal statistics into a first group of signal statistics or a second group of signal statistics based on time constants of the signal statistics; decimate the first group of signal statistics; generate a first predistortion term based on the decimated first group of signal statistics; generate a second predistortion term based on the second group of signal statistics; and generate an output predistortion terminal based on the first predistortion term and the second predistortion term.

公开(公告)号：US10924320B2

公开(公告)日：2021-02-16

申请号：US16525103

申请日：2019-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sthanunathan Ramakrishnan ,  Chandrasekhar Sriram ,  Raju Kharataram Chaudhari

IPC: H04L27/36 ,  H03D3/00 ,  H04B1/30 ,  H04L27/38

Abstract: An IQ estimation module comprising a powerup state IQ estimator configured to generate powerup state IQ estimates based on a powerup calibration of the IQ estimation module, a steady state IQ estimator configured to generate steady state IQ estimates during a steady state operation of the IQ estimation module, and an IQ estimate extender configured to determine differences between the powerup state IQ estimates and steady state IQ estimates at their respective frequency bins and adjust the powerup state IQ estimates to improve the accuracy of IQ estimates.

公开(公告)号：US10812294B2

公开(公告)日：2020-10-20

申请号：US16684842

申请日：2019-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Sashidharan Venkatraman ,  Sarma Sundareswara Gunturi ,  Chandrasekhar Sriram ,  Sthanunathan Ramakrishnan ,  Ram Narayan Krishna Nama Mony

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/02 ,  H04B1/02 ,  H04B17/11

Abstract: A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.

公开(公告)号：US20190013795A1

公开(公告)日：2019-01-10

申请号：US16005673

申请日：2018-06-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  KARTHIK KHANNA S ,  Chandrasekhar Sriram ,  Rajendrakumar Joish ,  Viswanathan Nagarajan

IPC: H03H11/12 ,  H03H11/06 ,  H01P1/22

CPC classification number: H03H11/1204 ,  H01P1/22 ,  H03H11/06 ,  H03H17/02 ,  H03H2011/0494 ,  H03M1/12

Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

公开(公告)号：US09935645B1

公开(公告)日：2018-04-03

申请号：US15674175

申请日：2017-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Chandrasekhar Sriram

IPC: H03M1/12 ,  H03M1/08

CPC classification number: H03M1/08 ,  H03M1/06 ,  H03M1/0836 ,  H03M1/0854 ,  H03M1/1042

Abstract: Circuitry for correcting non-linearity of an analog-to-digital converter. A non-linearity correction system for an analog-to-digital converter (ADC) includes coefficient storage, coefficient transformation circuitry, and correction circuitry. The coefficient storage is encoded with a first set of coefficients for correcting non-linearity of the ADC at a first sampling rate. The coefficient transformation circuitry is coupled to the coefficient storage. The coefficient transformation circuitry is configured to generate a second set of coefficients for correcting non-linearity of the ADC at a different sampling rate. The correction circuitry is configured to apply the second set of coefficients to correct non-linearity in output of the ADC while the ADC is operating at the different sampling rate.