公开(公告)号：US10320405B2

公开(公告)日：2019-06-11

申请号：US15909378

申请日：2018-03-01

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/10 ,  H03M1/16 ,  H03M1/36

Abstract: In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US20240187013A1

公开(公告)日：2024-06-06

申请号：US18440113

申请日：2024-02-13

Applicant: Texas Instruments Incorporated

Inventor： Himanshu Varshney ,  Viswanathan Nagarajan ,  Charls Babu ,  Narasimhan Rajagopal ,  Eeshan Miglani ,  Visvesvaraya A. Pentakota

IPC: H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/1009 ,  H03M1/002 ,  H03M1/10 ,  H03M1/12

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

公开(公告)号：US11962318B2

公开(公告)日：2024-04-16

申请号：US17568972

申请日：2022-01-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Himanshu Varshney ,  Viswanathan Nagarajan ,  Charls Babu ,  Narasimhan Rajagopal ,  Eeshan Miglani ,  Visvesvaraya A Pentakota

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/1009 ,  H03M1/002 ,  H03M1/10 ,  H03M1/12

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

公开(公告)号：US20170302287A1

公开(公告)日：2017-10-19

申请号：US15485552

申请日：2017-04-12

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1205 ,  H03M1/164 ,  H03M1/361

Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US20250004049A1

公开(公告)日：2025-01-02

申请号：US18217292

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Nithin Gopinath ,  Sai Aditya Nurani ,  Viswanathan Nagarajan ,  Himanshu Varshney ,  Mishab I ,  Mujammil Patel

IPC: G01R31/317

Abstract: An example apparatus includes programmable circuitry configured to: determine a first output voltage from a first analog to digital converter (ADC) responsive to the first ADC and a second ADC both receiving a first input voltage; determine a first output voltage from a second ADC responsive to the first ADC and a second ADC both receiving the first input voltage; determine a second output voltage from the first ADC responsive to the first ADC receiving a second input voltage and the second ADC receiving the first input voltage; and determine an error value for the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

公开(公告)号：US12074607B2

公开(公告)日：2024-08-27

申请号：US17825864

申请日：2022-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Nithin Gopinath ,  Viswanathan Nagarajan ,  Neeraj Shrivastava ,  Visvesvaraya A. Pentakota ,  Harshit Moondra ,  Abhinav Chandra

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

公开(公告)号：US10541700B2

公开(公告)日：2020-01-21

申请号：US16249225

申请日：2019-01-16

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Narasimhan Rajagopal ,  Shagun Dusad ,  Viswanathan Nagarajan ,  Visvesvaraya Appala Pentakota

IPC: H03M1/06 ,  H03M1/04 ,  H03M1/16

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

公开(公告)号：US20190013795A1

公开(公告)日：2019-01-10

申请号：US16005673

申请日：2018-06-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  KARTHIK KHANNA S ,  Chandrasekhar Sriram ,  Rajendrakumar Joish ,  Viswanathan Nagarajan

IPC: H03H11/12 ,  H03H11/06 ,  H01P1/22

CPC classification number: H03H11/1204 ,  H01P1/22 ,  H03H11/06 ,  H03H17/02 ,  H03H2011/0494 ,  H03M1/12

Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

公开(公告)号：US11955984B2

公开(公告)日：2024-04-09

申请号：US17828967

申请日：2022-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Viswanathan Nagarajan ,  Aniket Datta ,  Nithin Gopinath

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

公开(公告)号：US11881867B2

公开(公告)日：2024-01-23

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

CPC classification number: H03M1/1019

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.