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公开(公告)号：US11645083B2
公开(公告)日：2023-05-09
申请号：US13974571
申请日：2013-08-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Christian Wiencke , Shrey Sudhir Bhatia , Jeroen Vilegen
IPC: G06F9/38
CPC classification number: G06F9/3873 , G06F9/3838
Abstract: A system and method for reducing pipeline latency. In one embodiment, a processing system includes a processing pipeline. The processing pipeline includes a plurality of processing stages. Each stage is configured to further processing provided by a previous stage. A first of the stages is configured to perform a first function in a pipeline cycle. A second of the stages is disposed downstream of the first of the stages, and is configured to perform, in a pipeline cycle, a second function that is different from the first function. The first of the stages is further configured to selectably perform the first function and the second function in a pipeline cycle, and bypass the second of the stages.
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公开(公告)号：US20220100522A1
公开(公告)日：2022-03-31
申请号：US17550572
申请日：2021-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Christian Wiencke , Johann Zipperer
Abstract: A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the execution pipeline. The maximum number is based on a value contained in a pre-fetch threshold field of an instruction executed in the execution pipeline.
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公开(公告)号：US20210133065A1
公开(公告)日：2021-05-06
申请号：US17146584
申请日：2021-01-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shrey Bhatia , Christian Wiencke , Armin Stingl , Ralph Ledwa , Wolfgang Lutsch
IPC: G06F11/273 , G06F11/36 , G06F11/34 , G06F11/30 , G06F11/26
Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.
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公开(公告)号：US20210004236A1
公开(公告)日：2021-01-07
申请号：US17029299
申请日：2020-09-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Markus Koesler , Johann Zipperer , Christian Wiencke , Wolfgang Lutsch
IPC: G06F9/38 , G06F11/36 , G06F11/267 , G06F9/30
Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.
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公开(公告)号：US10437596B2
公开(公告)日：2019-10-08
申请号：US14554709
申请日：2014-11-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Christian Wiencke , Shrey Bhatia
Abstract: An apparatus and method system and method for increasing performance in a processor or other instruction execution device while minimizing energy consumption. A processor includes a first execution pipeline and a second execution pipeline. The first execution pipeline includes a first decode unit and a first execution control unit coupled to the first decode unit. The first execution control unit is configured to control execution of all instructions executable by the processor. The second execution pipeline includes a second decode unit, and a second execution control unit coupled to the second decode unit. The second execution control unit is configured to control execution of a subset of the instructions executable via the first execution control unit.
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Patent Agency Ranking
公开(公告)号：US20180349241A1
公开(公告)日：2018-12-06
申请号：US16102193
申请日：2018-08-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shrey Bhatia , Christian Wiencke , Armin Stingl , Ralph Ledwa , Wolfgang Lutsch
IPC: G06F11/273 , G06F11/30 , G06F11/36 , G06F11/34
CPC classification number: G06F11/273 , G06F11/3024 , G06F11/3089 , G06F11/348 , G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F11/3664 , Y02D10/34
Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.
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公开(公告)号：US20180349097A1
公开(公告)日：2018-12-06
申请号：US16056115
申请日：2018-08-06
Applicant: Texas Instruments Incorporated
Inventor： Christian Wiencke , Armin Stingl
CPC classification number: G06F7/44 , G06F7/42 , G06F7/5324
Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.
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公开(公告)号：US11861367B2
公开(公告)日：2024-01-02
申请号：US17550572
申请日：2021-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Christian Wiencke , Johann Zipperer
CPC classification number: G06F9/3814 , G06F9/30047 , G06F9/3804
Abstract: A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the execution pipeline. The maximum number is based on a value contained in a pre-fetch threshold field of an instruction executed in the execution pipeline.
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公开(公告)号：US11803455B2
公开(公告)日：2023-10-31
申请号：US18175607
申请日：2023-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shrey Bhatia , Christian Wiencke , Armin Stingl , Ralph Ledwa , Wolfgang Lutsch
CPC classification number: G06F11/273 , G06F11/26 , G06F11/3024 , G06F11/3089 , G06F11/348 , G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F11/3664
Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.
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公开(公告)号：US20230273797A1
公开(公告)日：2023-08-31
申请号：US18314264
申请日：2023-05-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Christian Wiencke , Shrey Sudhir Bhatia , Jeroen Vliegen
IPC: G06F9/38
CPC classification number: G06F9/3873 , G06F9/3838
Abstract: A system and method for reducing pipeline latency. In one embodiment, a processing system includes a processing pipeline. The processing pipeline includes a plurality of processing stages. Each stage is configured to further processing provided by a previous stage. A first of the stages is configured to perform a first function in a pipeline cycle. A second of the stages is disposed downstream of the first of the stages, and is configured to perform, in a pipeline cycle, a second function that is different from the first function. The first of the stages is further configured to selectably perform the first function and the second function in a pipeline cycle, and bypass the second of the stages.
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