Abstract:
Methods, apparatus, systems, and articles of manufacture are described corresponding to wide bandwidth hall sensing circuitry. An example circuit includes a first hall effect sensor configured to output a first voltage corresponding to a magnetic field; an amplifier to output an amplified voltage by amplifying the first voltage; a second hall effect sensor configured to output a second voltage corresponding to the magnetic field, the second hall effect sensor operating using a spinning technique to toggle a bias current between terminals of the second hall effect sensor, the spinning technique to remove a first offset corresponding to the second hall effect sensor; and offset reduction circuitry configured to: determine a second offset corresponding to the first hall effect sensor based on the first voltage and the second voltage; and generate an output based on the second offset, the amplifier to adjust the amplified voltage based on the output.
Abstract:
A system comprises a calibration current generator, which provides a calibration current to a first and a second Hall channel, and a bias current generator, which determines a difference between a calibration signal from the Hall channels and a threshold and adjusts a biasing current for the Hall channels based on the difference. In some embodiments, the bias current generator comprises a subtractor coupled to an ADC and a controller coupled between the ADC and a DAC. The subtractor obtains a first and a second signal from the first and second Hall channels, respectively, and subtracts the first from the second to obtain the calibration signal. The controller determines the difference between a sampled signal from the ADC and the threshold and an adjustment to the biasing current based on the difference. The DAC adjusts the biasing current based on a control signal from the controller indicating the adjustment.
Abstract:
In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.
Abstract:
An integrated circuit and method are provided for accurately measuring the temperature of a die of the integrated circuit. Pairs of diodes are driven with different currents in order to generate a series of thermal voltages. The ADC measures the series of thermal voltages against an external reference voltage. Based on these thermal voltage measurements, the ADC calculates the die temperature. The different currents used to generate the series of thermal voltages are selected at specific ratios to each other in order to promote the ability of the ability of the ADC to calculate the die temperature using standard components and logic of an ADC. These thermal voltages are generated and measured using integrated components of the die for which a temperature measurement is being provided, thus reducing several sources of inaccuracies in conventional die temperature measurement techniques. Addition embodiments are provided for detecting defective diodes based on comparisons of the thermal voltage outputs.
Abstract:
In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.
Abstract:
An integrated circuit and method are provided for accurately measuring the temperature of a die of the integrated circuit. Pairs of diodes are driven with different currents in order to generate a series of thermal voltages. The ADC measures the series of thermal voltages against an external reference voltage. Based on these thermal voltage measurements, the ADC calculates the die temperature. The different currents used to generate the series of thermal voltages are selected at specific ratios to each other in order to promote the ability of the ability of the ADC to calculate the die temperature using standard components and logic of an ADC. These thermal voltages are generated and measured using integrated components of the die for which a temperature measurement is being provided, thus reducing several sources of inaccuracies in conventional die temperature measurement techniques. Addition embodiments are provided for detecting defective diodes based on comparisons of the thermal voltage outputs.