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公开(公告)号：US10003306B1
公开(公告)日：2018-06-19
申请号：US15467417
申请日：2017-03-23
Applicant: Texas Instruments Incorporated
Inventor： Tony Ray Larson , Dimitar Trifonov Trifonov , Biraja Prasad Dash
CPC classification number: H03F1/26 , H03F3/387 , H03F3/45475 , H03F3/45968 , H03F2200/171 , H03F2200/271 , H03F2200/375 , H03F2200/459
Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.
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公开(公告)号：US11333719B2
公开(公告)日：2022-05-17
申请号：US17015347
申请日：2020-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Keith Ryan Green , Dimitar Trifonov , Tony Ray Larson
Abstract: A semiconductor device includes first and second Hall-effect sensors. Each sensor has first and third opposite terminals and second and fourth opposite terminals. A control circuit is configured to direct a current through the first and second sensors and to measure a corresponding Hall voltage of the first and second sensors. Directing includes applying a first source voltage in a first direction between the first and third terminals of the first sensor and applying a second source voltage in a second direction between the first and third terminals of the second sensor. A third source voltage is applied in a third direction between the second and fourth terminals of the first sensor, and a fourth source voltage is applied in a fourth direction between the second and fourth terminals of the second sensor. The third direction is rotated clockwise from the first direction and the fourth direction rotated counter-clockwise from the second direction.
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公开(公告)号：US10892405B2
公开(公告)日：2021-01-12
申请号：US16404978
申请日：2019-05-07
Applicant: Texas Instruments Incorporated
Inventor： Ming Li , Yiqi Tang , Jie Chen , Enis Tuncer , Usman Mahmood Chaudhry , Tony Ray Larson , Rajen Manicon Murugan , John Paul Tellkamp , Satyendra Singh Chauhan
Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
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公开(公告)号：US11899082B2
公开(公告)日：2024-02-13
申请号：US17015327
申请日：2020-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Keith Ryan Green , Tony Ray Larson
CPC classification number: G01R33/072 , H10N52/101 , H10N52/80 , H10N52/01
Abstract: An integrated circuit includes a doped region having a first conductivity type formed in a semiconductor substrate having a second conductivity type. A dielectric layer is located between the doped region and a surface plane of the semiconductor substrate, and a polysilicon layer is located over the dielectric layer. First, second, third and fourth terminals are connected to the doped region, the first and third terminals defining a conductive path through the doped region and the second and fourth terminals defining a second conductive path through the doped region, the second path intersecting the first path.
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公开(公告)号：US10483920B2
公开(公告)日：2019-11-19
申请号：US15982666
申请日：2018-05-17
Applicant: Texas Instruments Incorporated
Inventor： Tony Ray Larson , Dimitar Trifonov Trifonov , Biraja Prasad Dash
Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.
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Patent Agency Ranking
公开(公告)号：US20220075007A1
公开(公告)日：2022-03-10
申请号：US17015347
申请日：2020-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Keith Ryan Green , Dimitar Trifonov , Tony Ray Larson
Abstract: A semiconductor device includes first and second Hall-effect sensors. Each sensor has first and third opposite terminals and second and fourth opposite terminals. A control circuit is configured to direct a current through the first and second sensors and to measure a corresponding Hall voltage of the first and second sensors. Directing includes applying a first source voltage in a first direction between the first and third terminals of the first sensor and applying a second source voltage in a second direction between the first and third terminals of the second sensor. A third source voltage is applied in a third direction between the second and fourth terminals of the first sensor, and a fourth source voltage is applied in a fourth direction between the second and fourth terminals of the second sensor. The third direction is rotated clockwise from the first direction and the fourth direction rotated counter-clockwise from the second direction.
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公开(公告)号：US20210159403A1
公开(公告)日：2021-05-27
申请号：US17142539
申请日：2021-01-06
Applicant: Texas Instruments Incorporated
Inventor： Ming Li , Yiqi Tang , Jie Chen , Enis Tuncer , Usman Mahmood Chaudhry , Tony Ray Larson , Rajen Manicon Murugan , John Paul Tellkamp , Satyendra Singh Chauhan
IPC: H01L43/14 , H01L43/06 , G01R15/20 , H01L23/495 , G01R33/07
Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
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公开(公告)号：US11867773B2
公开(公告)日：2024-01-09
申请号：US16888927
申请日：2020-06-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Partha Sarathi Basu , Dimitar Trifonov Trifonov , Tony Ray Larson , Chao-Hsiuan Tsay
CPC classification number: G01R33/0017 , G01R33/072 , G06G7/184
Abstract: A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.
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公开(公告)号：US11557722B2
公开(公告)日：2023-01-17
申请号：US17142539
申请日：2021-01-06
Applicant: Texas Instruments Incorporated
Inventor： Ming Li , Yiqi Tang , Jie Chen , Enis Tuncer , Usman Mahmood Chaudhry , Tony Ray Larson , Rajen Manicon Murugan , John Paul Tellkamp , Satyendra Singh Chauhan
Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
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公开(公告)号：US20220075009A1
公开(公告)日：2022-03-10
申请号：US17015327
申请日：2020-09-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Keith Ryan Green , Tony Ray Larson
Abstract: An integrated circuit includes a doped region having a first conductivity type formed in a semiconductor substrate having a second conductivity type. A dielectric layer is located between the doped region and a surface plane of the semiconductor substrate, and a polysilicon layer is located over the dielectric layer. First, second, third and fourth terminals are connected to the doped region, the first and third terminals defining a conductive path through the doped region and the second and fourth terminals defining a second conductive path through the doped region, the second path intersecting the first path.
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