GAIN AND TEMPERATURE TOLERANT BANDGAP VOLTAGE REFERENCE

    公开(公告)号:US20240103558A1

    公开(公告)日:2024-03-28

    申请号:US17950276

    申请日:2022-09-22

    CPC classification number: G05F3/265

    Abstract: Examples of bandgap circuits and elements thereof enable generation of an accurate and stable bandgap reference voltage that is not affected by low current gain. An example circuit includes first and second input transistors, each having an emitter to receive a tail current; first and second core transistors, a collector of each coupled to ground; a first lower leg coupled between a first upper leg and the emitter of the first core transistor at a first current input coupled to the base of the first input transistor; a second lower leg coupled between a second upper leg and the emitter of the second core transistor at a second current input coupled to the base of the second input transistor; and a base resistor coupled between the base and collector of the first core transistor. The input transistor pair has a current density ratio that is the same as that of the core transistor pair.

    AMPLIFIER WITH INPUT AND OUTPUT COMMON-MODE CONTROL IN A SINGLE AMPLIFICATION STAGE

    公开(公告)号:US20240339977A1

    公开(公告)日:2024-10-10

    申请号:US18498492

    申请日:2023-10-31

    CPC classification number: H03F3/45381 H03F3/45636 H03F2203/45008

    Abstract: In some examples, an amplifier includes a pair of input differential transistors a pair of feedback transistors, a pair of current sources, a pair of gain setting resistors, and a tail current transistor. Control terminals of the feedback transistors are respectively coupled to first terminals of the input differential transistors. The pair of current sources are respectively coupled to the control terminals of the feedback transistors and the first terminals of the input differential transistors. The pair of gain setting resistors have first terminals that are respectively coupled to the second terminals of the input differential transistors. The pair of gain setting resistors have second terminals that are coupled to one another. The tail current transistor has a first terminal coupled to the second terminals of the gain setting resistors and a second terminal coupled to a DC supply.

    HALL-EFFECT SENSOR WITH REDUCED OFFSET VOLTAGE

    公开(公告)号:US20220075007A1

    公开(公告)日:2022-03-10

    申请号:US17015347

    申请日:2020-09-09

    Abstract: A semiconductor device includes first and second Hall-effect sensors. Each sensor has first and third opposite terminals and second and fourth opposite terminals. A control circuit is configured to direct a current through the first and second sensors and to measure a corresponding Hall voltage of the first and second sensors. Directing includes applying a first source voltage in a first direction between the first and third terminals of the first sensor and applying a second source voltage in a second direction between the first and third terminals of the second sensor. A third source voltage is applied in a third direction between the second and fourth terminals of the first sensor, and a fourth source voltage is applied in a fourth direction between the second and fourth terminals of the second sensor. The third direction is rotated clockwise from the first direction and the fourth direction rotated counter-clockwise from the second direction.

    Current sense amplifier
    4.
    发明授权

    公开(公告)号:US12081182B2

    公开(公告)日:2024-09-03

    申请号:US18049831

    申请日:2022-10-26

    Abstract: A current sense amplifier includes a first amplifier stage, a second amplifier stage, a switch, and a common-mode transient detector. The first amplifier stage has a first amplifier output, a second amplifier output, a first amplifier input, and a second amplifier input. The second amplifier stage has a third amplifier input coupled to the first amplifier output, and a fourth amplifier input coupled to the second amplifier output. The switch has a switch control input, a first switch terminal coupled to the third amplifier input, and a second switch terminal coupled to the fourth amplifier input. The common-mode transient detector circuit has a detector output, a first detector input and a second detector input. The detector output is coupled to the switch control input. The first detector input is coupled to the first amplifier input. The second detector input is coupled to the second amplifier input.

    METHODS AND APPARATUS TO IMPROVE DIFFERENCE AMPLIFIERS

    公开(公告)号:US20240146265A1

    公开(公告)日:2024-05-02

    申请号:US17977840

    申请日:2022-10-31

    CPC classification number: H03F3/45475 H03F2203/45594

    Abstract: An example apparatus includes: a differential amplifier including: an inverting input coupled to a first input via a first resistor; a non-inverting input coupled to a second input via a second resistor; a first supply input coupled to the first input via a third resistor, and the first supply input coupled to the second input via a fourth resistor; a second supply input coupled to a current source; a non-inverting output; and an inverting output; a first transistor including a first control terminal and a first current terminal, the first control terminal coupled to the non-inverting output and the first current terminal coupled to the inverting input; and a second transistor including a second control terminal and a second current terminal, the second control terminal coupled to the inverting output and the second current terminal coupled to the non-inverting input.

    Hall Effect Sensor with Reduced JFET Effect

    公开(公告)号:US20230048022A1

    公开(公告)日:2023-02-16

    申请号:US17402019

    申请日:2021-08-13

    Abstract: A Hall effect sensor including a Hall element disposed at a surface of a semiconductor body, including a first doped region of a first conductivity type disposed over and abutted by an isolated second doped region of a second conductivity type. First through fourth terminals of the Hall element are in electrical contact with the first doped region, and a fifth terminal in electrical contact with the second doped region. A Hall effect sensor includes a first current source coupled to the first terminal of the Hall element, and common mode feedback regulation circuitry. The common mode feedback regulation circuitry has an output coupled to the third terminal and a ground node, and having an input coupled to the second and fourth terminals of the Hall element, and an output coupled to the third terminal and a ground node, where the second doped region is coupled to the third terminal.

    Hall-effect sensor with reduced offset voltage

    公开(公告)号:US11333719B2

    公开(公告)日:2022-05-17

    申请号:US17015347

    申请日:2020-09-09

    Abstract: A semiconductor device includes first and second Hall-effect sensors. Each sensor has first and third opposite terminals and second and fourth opposite terminals. A control circuit is configured to direct a current through the first and second sensors and to measure a corresponding Hall voltage of the first and second sensors. Directing includes applying a first source voltage in a first direction between the first and third terminals of the first sensor and applying a second source voltage in a second direction between the first and third terminals of the second sensor. A third source voltage is applied in a third direction between the second and fourth terminals of the first sensor, and a fourth source voltage is applied in a fourth direction between the second and fourth terminals of the second sensor. The third direction is rotated clockwise from the first direction and the fourth direction rotated counter-clockwise from the second direction.

    Level shifter circuit generating bipolar clock signals

    公开(公告)号:US10587267B2

    公开(公告)日:2020-03-10

    申请号:US16402262

    申请日:2019-05-03

    Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

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