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    Nonlinear class AB input stage
    1.
    发明授权
    Nonlinear class AB input stage 有权

    公开(公告)号：US10033342B2

    公开(公告)日：2018-07-24

    申请号：US15437258

    申请日：2017-02-20

    Applicant: Texas Instruments Incorporated

    Inventor： Vadim V. Ivanov ,  Ravinthiran Balasingam

    IPC: H03F3/45 ,  H03G3/30 ,  H03F1/34 ,  H03F3/21

    Abstract: A circuit includes a differential input stage amplifier that receives a differential input voltage and generates an output voltage based on a difference in the differential input voltage. A feedback loop provides feedback from an output of the differential input stage amplifier to input tail current of the differential input stage amplifier. The feedback loop enables class AB operation of the differential input stage amplifier. At least one gain reducer is operatively coupled to the feedback loop to reduce the gain of the feedback loop. The gain reducer has a resistance value that varies inversely proportional to loop current in the feedback loop to reduce the gain of the feedback loop as loop current increases.

    Level shifter circuit generating bipolar clock signals
    3.
    发明授权
    Level shifter circuit generating bipolar clock signals 有权

    公开(公告)号：US10979052B2

    公开(公告)日：2021-04-13

    申请号：US16774018

    申请日：2020-01-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Biraja Prasad Dash ,  Ravinthiran Balasingam ,  Dimitar Trifonov

    IPC: H03K19/0175 ,  H03K19/0185 ,  H03K3/356

    Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

    Level shifter circuit generating bipolar clock signals
    4.
    发明授权
    Level shifter circuit generating bipolar clock signals 有权

    公开(公告)号：US10326451B2

    公开(公告)日：2019-06-18

    申请号：US16101699

    申请日：2018-08-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Biraja Prasad Dash ,  Ravinthiran Balasingam ,  Dimitar Trifonov

    IPC: H03L5/00 ,  H03K19/0185 ,  H03K3/356

    Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

    LOAD DEPENDENT BIASING CELL FOR LOW DROPOUT REGULATOR
    5.
    发明申请
    LOAD DEPENDENT BIASING CELL FOR LOW DROPOUT REGULATOR 审中-公开
    用于低压差稳压器的负载相关偏置单元

    公开(公告)号：US20150227147A1

    公开(公告)日：2015-08-13

    申请号：US14619900

    申请日：2015-02-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： VADIM V. IVANOV ,  Ravinthiran Balasingam

    IPC: G05F1/575

    CPC classification number: G05F1/575

    Abstract: A circuit includes an error amplifier having a reference input that receives a reference voltage, a load feedback input that receives feedback from an output voltage, and a bias feedback input that receives a current to set a transconductance for the error amplifier. The error amplifier generates an error output signal to control an output voltage and load current of a low dropout (LDO) linear regulator based on a voltage difference between the load feedback input and the reference input. A bias adjuster monitors a load current generated by the LDO linear regulator and controls a bias current supplied to the bias feedback input of the error amplifier to control the transconductance of the error amplifier such that the transconductance of the error amplifier substantially tracks a transconductance of an output pass device supplying the output voltage and load current generated by the LDO linear regulator.

    Abstract translation: 电路包括具有接收参考电压的参考输入的误差放大器，从输出电压接收反馈的负载反馈输入和接收电流以设置误差放大器的跨导的偏置反馈输入。 误差放大器基于负载反馈输入和参考输入之间的电压差产生误差输出信号，以控制低压差（LDO）线性稳压器的输出电压和负载电流。 偏置调节器监视由LDO线性稳压器产生的负载电流，并控制提供给误差放大器的偏置反馈输入的偏置电流，以控制误差放大器的跨导，使得误差放大器的跨导基本上跟踪 输出通过器件提供由LDO线性稳压器产生的输出电压和负载电流。

    Level shifter circuit generating bipolar clock signals
    6.
    发明授权
    Level shifter circuit generating bipolar clock signals 有权

    公开(公告)号：US10587267B2

    公开(公告)日：2020-03-10

    申请号：US16402262

    申请日：2019-05-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Biraja Prasad Dash ,  Ravinthiran Balasingam ,  Dimitar Trifonov

    IPC: H03L5/00 ,  H03K3/356 ,  H03K19/0185

    Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

    Nonlinear class AB input stage
    8.
    发明授权
    Nonlinear class AB input stage 有权
    非线性AB类输入级

    公开(公告)号：US09577589B2

    公开(公告)日：2017-02-21

    申请号：US14619860

    申请日：2015-02-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Vadim V. Ivanov ,  Ravinthiran Balasingam

    IPC: H03F3/45 ,  H03F1/34 ,  H03F3/21 ,  H03F1/08 ,  H03G1/00

    CPC classification number: H03G3/30 ,  H03F1/086 ,  H03F1/34 ,  H03F3/21 ,  H03F3/45183 ,  H03F3/45273 ,  H03F3/45475 ,  H03F2200/123 ,  H03F2200/129 ,  H03F2200/153 ,  H03F2203/45116 ,  H03F2203/45264 ,  H03G1/0035

    Abstract: A circuit includes a differential input stage amplifier that receives a differential input voltage and generates an output voltage based on a difference in the differential input voltage. A feedback loop provides feedback from an output of the differential input stage amplifier to input tail current of the differential input stage amplifier. The feedback loop enables class AB operation of the differential input stage amplifier. At least one gain reducer is operatively coupled to the feedback loop to reduce the gain of the feedback loop. The gain reducer has a resistance value that varies inversely proportional to loop current in the feedback loop to reduce the gain of the feedback loop as loop current increases.

    Abstract translation: 电路包括差分输入级放大器，其接收差分输入电压并且基于差分输入电压的差产生输出电压。 反馈环路提供来自差分输入级放大器的输出的反馈以输入差分输入级放大器的尾部电流。 反馈环路使得差分输入级放大器的AB类工作成为可能。 至少一个增益减小器可操作地耦合到反馈回路以减小反馈回路的增益。 增益减小器具有与反馈环路中的回路电流成反比的电阻值，以在环路电流增加时降低反馈回路的增益。

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