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公开(公告)号：US10483920B2
公开(公告)日：2019-11-19
申请号：US15982666
申请日：2018-05-17
Applicant: Texas Instruments Incorporated
Inventor： Tony Ray Larson , Dimitar Trifonov Trifonov , Biraja Prasad Dash
Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.
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公开(公告)号：US10003306B1
公开(公告)日：2018-06-19
申请号：US15467417
申请日：2017-03-23
Applicant: Texas Instruments Incorporated
Inventor： Tony Ray Larson , Dimitar Trifonov Trifonov , Biraja Prasad Dash
CPC classification number: H03F1/26 , H03F3/387 , H03F3/45475 , H03F3/45968 , H03F2200/171 , H03F2200/271 , H03F2200/375 , H03F2200/459
Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.
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Patent Agency Ranking
公开(公告)号：US10587267B2
公开(公告)日：2020-03-10
申请号：US16402262
申请日：2019-05-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Biraja Prasad Dash , Ravinthiran Balasingam , Dimitar Trifonov
IPC: H03L5/00 , H03K3/356 , H03K19/0185
Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.
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公开(公告)号：US10530302B2
公开(公告)日：2020-01-07
申请号：US16042436
申请日：2018-07-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ravinthiran Balasingam , Dimitar Trifonov , Biraja Prasad Dash
Abstract: A circuit, comprising an input chopper configured to receive an input signal, a differential amplifier having an input coupled to an output of the input chopper, a current mode chopping circuit coupled to an output of the differential amplifier, and a first current mirror bias transistor pair coupled between a voltage supply and the current mode chopping circuit.
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公开(公告)号：US10979052B2
公开(公告)日：2021-04-13
申请号：US16774018
申请日：2020-01-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Biraja Prasad Dash , Ravinthiran Balasingam , Dimitar Trifonov
IPC: H03K19/0175 , H03K19/0185 , H03K3/356
Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.
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公开(公告)号：US10326451B2
公开(公告)日：2019-06-18
申请号：US16101699
申请日：2018-08-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Biraja Prasad Dash , Ravinthiran Balasingam , Dimitar Trifonov
IPC: H03L5/00 , H03K19/0185 , H03K3/356
Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.
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公开(公告)号：US20180337639A1
公开(公告)日：2018-11-22
申请号：US15982666
申请日：2018-05-17
Applicant: Texas Instruments Incorporated
Inventor： Tony Ray Larson , Dimitar Trifonov Trifonov , Biraja Prasad Dash
CPC classification number: H03F1/26 , H03F3/387 , H03F3/45475 , H03F3/45968 , H03F2200/171 , H03F2200/271 , H03F2200/375 , H03F2200/459
Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.
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