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11.发明申请公开(公告)号：US20190197718A1
公开(公告)日：2019-06-27
申请号：US16291405
申请日：2019-03-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jayasree Sankaranarayanan , Dipan Kumar Mandal
CPC classification number: G06T7/60 , G06F9/3001 , G06F9/30036 , G06F9/3012 , G06F9/3013 , G06F9/3887 , G06F9/3891 , G06F17/16 , G06T1/20 , G06T2200/28
Abstract: Disclosed techniques relate to forming a block sum of picture elements employing a vector dot product instruction to sum packed picture elements and the mask producing a vector of masked horizontal picture element. The block sum is formed from plural horizontal sums via vector single instruction multiple data (SIMD) addition.
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公开(公告)号：US09973754B2
公开(公告)日：2018-05-15
申请号：US14661711
申请日：2015-03-18
Applicant: Texas Instruments Incorporated
Inventor： Hetul Sanghvi , Mihir Narendra Mody , Niraj Nandan , Mahesh Madhukar Mehendale , Subrangshu Das , Dipan Kumar Mandal , Pavan Venkata Shastry
IPC: H04N19/115 , H04N19/423 , G06F13/28
CPC classification number: H04N19/115 , G06F13/28 , H04N19/423
Abstract: A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N.
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13.发明申请METHOD FOR PERFORMING RANDOM READ ACCESS TO A BLOCK OF DATA USING PARALLEL LUT READ INSTRUCTION IN VECTOR PROCESSORS 审中-公开使用并行处理器中的并行LUT读取指令执行随机读取访问数据块的方法公开(公告)号：US20160124651A1
公开(公告)日：2016-05-05
申请号：US14920365
申请日：2015-10-22
Applicant: Texas Instruments Incorporated
Inventor： Jayasree Sankaranarayanan , Dipan Kumar Mandal
CPC classification number: G06F9/383 , G06F9/30036 , G06F9/3004 , G06F9/30043
Abstract: This invention deals with the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.
Abstract translation: 本发明涉及在用于向量SIMD处理器的合理大小的数据块内并行随机读取访问的问题。 本发明设置多个并行查找表，将数据从主存储器移动到每个多个并行查找表，然后使用查找表读取指令来同时将数据从每个并行查找表移动到相应部分的向量目标寄存器。 这使得能够通过矢量单指令多数据（SIMD）操作进行数据处理。 如果表存储更多使用的数据，则可以重复此向量目标寄存器加载。 如果适用，新数据可以加载到原始表中。 一级存储器优选地被分割为部分数据高速缓存和部分直接可寻址存储器。 查找表存储器存储在可直接寻址的存储器中。
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14.发明申请公开(公告)号：US20160062869A1
公开(公告)日：2016-03-03
申请号：US14936970
申请日：2015-11-10
Applicant: Texas Instruments Incorporated
Inventor： Kanika Ghai Bansal , Dipan Kumar Mandal , Gary A. Cooper , Bryan J. Thome
CPC classification number: G06F11/3466 , G06F9/542 , G06F11/3476 , G06F11/348 , G06F11/3636
Abstract: An electronic tracing process includes packing both stall (215) and reason (219) data into a single high priority timing information stream. An integrated circuit includes an electronic processor (110), and a tracing circuit (120) operable to pack both stall and events data into a single timing information stream. Other circuits, processes and systems are also disclosed.
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15.发明申请EMBEDDING STALL AND EVENT TRACE PROFILING DATA IN THE TIMING STREAM - EXTENDED TIMING TRACE CIRCUITS, PROCESSES, AND SYSTEMS 审中-公开嵌入式和事件跟踪时序流中的分析数据 - 扩展时序跟踪电路，过程和系统公开(公告)号：US20150149833A1
公开(公告)日：2015-05-28
申请号：US14559221
申请日：2014-12-03
Applicant: Texas Instruments Incorporated
Inventor： Kanika Ghai Bansal , Dipan Kumar Mandal , Gary A. Cooper , Bryan J. Thome
IPC: G06F11/34
CPC classification number: G06F11/3466 , G06F9/542 , G06F11/3476 , G06F11/348 , G06F11/3636
Abstract: An electronic tracing process includes packing both stall (215) and reason (219) data into a single high priority timing information stream. An integrated circuit includes an electronic processor (110), and a tracing circuit (120) operable to pack both stall and events data into a single timing information stream. Other circuits, processes and systems are also disclosed.
Abstract translation: 电子跟踪过程包括将失速（215）和原因（219）数据打包到单个高优先级定时信息流中。 集成电路包括电子处理器（110）和跟踪电路（120），可操作以将失速和事件数据分组到单个定时信息流中。 还公开了其它电路，过程和系统。
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Patent Agency Ranking
公开(公告)号：US09898805B2
公开(公告)日：2018-02-20
申请号：US15040424
申请日：2016-02-10
Applicant: Texas Instruments Incorporated
Inventor： Sanmati S. Kamath , Dipan Kumar Mandal , Wonki Choi
CPC classification number: G06T5/00 , G06F17/18 , G06T5/20 , G06T2200/28 , G06T2207/20032 , H03H17/0261
Abstract: A method is disclosed for efficiently calculating a median value of a high-order array in a Single Instruction Multiple Data (SIMD) processor. Values of the high-order array are sorted vertically in each column followed by sorts on each individual row. After the sort, selective diagonal values of the sorted high-order array are used to form a low-order array to calculate the median of the high-order array. The median calculation using selective diagonal values of the high-order array in a low-order array significantly improves SIMD processor efficiency and throughput.
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公开(公告)号：US09798645B2
公开(公告)日：2017-10-24
申请号：US14936970
申请日：2015-11-10
Applicant: Texas Instruments Incorporated
Inventor： Kanika Ghai Bansal , Dipan Kumar Mandal , Gary A. Cooper , Bryan J. Thome
CPC classification number: G06F11/3466 , G06F9/542 , G06F11/3476 , G06F11/348 , G06F11/3636
Abstract: An electronic tracing process includes packing both stall (215) and reason (219) data into a single high priority timing information stream. An integrated circuit includes an electronic processor (110), and a tracing circuit (120) operable to pack both stall and events data into a single timing information stream. Other circuits, processes and systems are also disclosed.
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公开(公告)号：US20170076173A1
公开(公告)日：2017-03-16
申请号：US15345523
申请日：2016-11-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: G06K9/4638 , G06K9/00986 , G06K9/4604 , G06K9/481 , G06K9/6211
Abstract: This invention enables effective corner detection of pixels of an image using the FAST algorithm using a vector SIMD processor. This invention loads an 8×8 pixel block that includes four 7×7 pixel blocks including the 16 peripheral pixels to be tested for each of four center pixels. This invention rearranges the 64 pixels of the 8×8 block to form a 16 element array for each center pixel preferably using a vector permutation instruction. This invention uses vector SIMD subtraction and compare and vector SIMD addition and compare to make the FAST algorithm comparisons. The N consecutive pixels determinations of the FAST algorithm are made from the results of plural shift and AND operations. The corresponding center pixel is marked a corner or not a corner dependent upon of the results of plural shift and AND operations.
Abstract translation: 本发明可以使用使用向量SIMD处理器的FAST算法来有效地角度检测图像的像素。 本发明加载包括四个7×7像素块的8×8像素块，包括要测试的四个中心像素中的每一个的16个外围像素。 本发明重新排列8×8块的64个像素，优选地使用向量置换指令来为每个中心像素形成16个元件阵列。 本发明使用矢量SIMD减法和比较和矢量SIMD加法比较，使得FAST算法比较。 FAST算法的N个连续像素确定由多个移位和“与”运算的结果进行。 取决于多个换档和“与”运算的结果，相应的中心像素被标记为拐角或不标记角。
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公开(公告)号：US20160125257A1
公开(公告)日：2016-05-05
申请号：US14581401
申请日：2014-12-23
Applicant: Texas Instruments Incorporated
CPC classification number: G06K9/4638 , G06K9/00986 , G06K9/4604 , G06K9/481 , G06K9/6211
Abstract: This invention enables effective corner detection of pixels of an image using the FAST algorithm using a vector SIMD processor. This invention loads an 8×8 pixel block that includes four 7×7 pixel blocks including the 16 peripheral pixels to be tested for each of four center pixels. This invention rearranges the 64 pixels of the 8×8 block to form a 16 element array for each center pixel preferably using a vector permutation instruction. This invention uses vector SIMD subtraction and compare and vector SIMD addition and compare to make the FAST algorithm comparisons. The N consecutive pixels determinations of the FAST algorithm are made from the results of plural shift and AND operations. The corresponding center pixel is marked a corner or not a corner dependent upon of the results of plural shift and AND operations.
Abstract translation: 本发明可以使用使用向量SIMD处理器的FAST算法来有效地角度检测图像的像素。 本发明加载包括四个7×7像素块的8×8像素块，包括要测试的四个中心像素中的每一个的16个外围像素。 本发明重新排列8×8块的64个像素，优选地使用向量置换指令来为每个中心像素形成16个元件阵列。 本发明使用矢量SIMD减法和比较和矢量SIMD加法比较，使得FAST算法比较。 FAST算法的N个连续像素确定由多个移位和“与”运算的结果进行。 取决于多个换档和“与”运算的结果，相应的中心像素被标记为拐角或不标记角。
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20.发明授权Introducing timing synchronization indicating stall reason in next synchronization window 有权在下一个同步窗口中引入时序同步指示失速原因公开(公告)号：US09223676B2
公开(公告)日：2015-12-29
申请号：US14559221
申请日：2014-12-03
Applicant: Texas Instruments Incorporated
Inventor： Kanika Ghai Bansal , Dipan Kumar Mandal , Gary A. Cooper , Bryan J. Thome
CPC classification number: G06F11/3466 , G06F9/542 , G06F11/3476 , G06F11/348 , G06F11/3636
Abstract: An electronic tracing process includes packing both stall (215) and reason (219) data into a single high priority timing information stream. An integrated circuit includes an electronic processor (110), and a tracing circuit (120) operable to pack both stall and events data into a single timing information stream. Other circuits, processes and systems are also disclosed.
Abstract translation: 电子跟踪过程包括将失速（215）和原因（219）数据打包到单个高优先级定时信息流中。 集成电路包括电子处理器（110）和跟踪电路（120），可操作以将失速和事件数据分组到单个定时信息流中。 还公开了其它电路，过程和系统。
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