公开(公告)号：US20250013467A1

公开(公告)日：2025-01-09

申请号：US18892682

申请日：2024-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR

IPC: G06F9/30 ,  G06F12/0811

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

公开(公告)号：US20230359385A1

公开(公告)日：2023-11-09

申请号：US18353181

申请日：2023-07-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Soujanya NARNUR

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/80

CPC classification number: G06F3/0652 ,  G06F13/1668 ,  G06F3/0673 ,  G06F3/0604 ,  G06F15/8076

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

公开(公告)号：US20230214220A1

公开(公告)日：2023-07-06

申请号：US18120601

申请日：2023-03-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR

IPC: G06F9/30 ,  G06F12/0811

CPC classification number: G06F9/3016 ,  G06F9/30065 ,  G06F12/0811 ,  G06F9/30098

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

公开(公告)号：US20200371711A1

公开(公告)日：2020-11-26

申请号：US16422250

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR ,  Alan DAVIS

IPC: G06F3/06 ,  G06F9/30

Abstract: A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

公开(公告)号：US20200371706A1

公开(公告)日：2020-11-26

申请号：US16422522

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Soujanya NARNUR

IPC: G06F3/06 ,  G06F13/16

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.