公开(公告)号：US09899484B1

公开(公告)日：2018-02-20

申请号：US15395015

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/41 ,  H01L29/45 ,  H01L29/49 ,  H01L27/06 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

公开(公告)号：US11355597B2

公开(公告)日：2022-06-07

申请号：US17153976

申请日：2021-01-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Tomomatsu ,  Sameer Pendharkar ,  Hiroshi Yamasaki

IPC: H01L23/48 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423 ,  H01L23/482 ,  H01L29/20

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

公开(公告)号：US10186589B2

公开(公告)日：2019-01-22

申请号：US15865746

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/41 ,  H01L29/45 ,  H01L29/49 ,  H01L27/06 ,  H01L29/417 ,  H01L29/778

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

公开(公告)号：US20180190778A1

公开(公告)日：2018-07-05

申请号：US15865746

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/778 ,  H01L27/06 ,  H01L29/417 ,  H01L29/20 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

公开(公告)号：US09818839B2

公开(公告)日：2017-11-14

申请号：US15237041

申请日：2016-08-15

Applicant: Texas Instruments Incorporated

Inventor： Yoshikazu Kondo ,  Shoji Wada ,  Hiroshi Yamasaki ,  Masahiro Iwamoto

IPC: H01L21/306 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L21/283 ,  H01L29/20 ,  H01L21/285

CPC classification number: H01L29/66462 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/30621 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452

Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

公开(公告)号：US20140302672A1

公开(公告)日：2014-10-09

申请号：US13856016

申请日：2013-04-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yoshikazu Kondo ,  Shoji Wada ,  Hiroshi Yamasaki ,  Masahiro Iwamoto

IPC: H01L21/283 ,  H01L21/306

CPC classification number: H01L29/66462 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/30621 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452

Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

Abstract translation: 金属接触开口在III-N HEMT的阻挡层中被蚀刻，其具有蚀刻到阻挡层中的第一气体组合，以及第二气体组合，其进一步向下蚀刻到阻挡层中至达顶部的深度 接触并位于阻挡层下方的通道层的表面。

公开(公告)号：US20210143258A1

公开(公告)日：2021-05-13

申请号：US17153976

申请日：2021-01-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Tomomatsu ,  Sameer Pendharkar ,  Hiroshi Yamasaki

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/423 ,  H01L23/482

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

公开(公告)号：US10510847B2

公开(公告)日：2019-12-17

申请号：US16213013

申请日：2018-12-07

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/41 ,  H01L29/45 ,  H01L29/49 ,  H01L29/778 ,  H01L27/06 ,  H01L29/417

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

公开(公告)号：US20190245047A1

公开(公告)日：2019-08-08

申请号：US16383857

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Tomomatsu ,  Sameer Pendharkar ,  Hiroshi Yamasaki

IPC: H01L29/40 ,  H01L23/482 ,  H01L29/778 ,  H01L29/423

CPC classification number: H01L29/404 ,  H01L23/4824 ,  H01L29/2003 ,  H01L29/4238 ,  H01L29/7786

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

公开(公告)号：US20190109195A1

公开(公告)日：2019-04-11

申请号：US16213013

申请日：2018-12-07

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/778 ,  H01L27/06 ,  H01L29/45 ,  H01L29/417 ,  H01L29/49 ,  H01L29/20

CPC classification number: H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.