公开(公告)号：US20200019374A1

公开(公告)日：2020-01-16

申请号：US16237447

申请日：2018-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu PRATHAPAN ,  Puneet SABBARWAL ,  Pankaj GUPTA

IPC: G06F7/24 ,  G06F5/06

Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

公开(公告)号：US20180189133A1

公开(公告)日：2018-07-05

申请号：US15653749

申请日：2017-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu PRATHAPAN ,  Prashanth SARAF ,  Desmond Pravin Martin FERNANDES ,  Saket JALAN

IPC: G06F11/10 ,  G11C5/04 ,  G06F3/06 ,  G11C11/16 ,  G11C11/56 ,  H03M13/35

CPC classification number: G06F11/1044 ,  G06F3/0653 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/108 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/5628 ,  G11C2207/2263 ,  G11C2207/229 ,  H03M13/19 ,  H03M13/35 ,  H03M13/356 ,  H03M13/3776

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.