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公开(公告)号：US20180173900A1
公开(公告)日：2018-06-21
申请号：US15898935
申请日：2018-02-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Joyce Kwong , Clive Bittlestone , Manish Goel
CPC classification number: G06F21/73 , G09C1/00 , G11C11/419 , G11C29/50012 , G11C2029/4402 , G11C2029/5002 , H04L9/3278
Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.
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公开(公告)号：US09934411B2
公开(公告)日：2018-04-03
申请号：US14798067
申请日：2015-07-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Joyce Kwong , Clive Bittlestone , Manish Goel
CPC classification number: G06F21/73 , G09C1/00 , G11C11/419 , G11C29/50012 , G11C2029/4402 , G11C2029/5002 , H04L9/3278
Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.
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Patent Agency Ranking
公开(公告)号：US20210109579A1
公开(公告)日：2021-04-15
申请号：US17130076
申请日：2020-12-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Clive Bittlestone , Joyce Kwong , Manish Goel
Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes decreasing a supply voltage of a memory array to a first voltage level, the first voltage level being below a normal operating voltage associated with the memory array, reading a first value of a bit cell after the supply voltage has been at the first voltage level, and determining a function based on the first value of the bit cell and a second value, the second value stored in the bit cell when the memory array is operating at a voltage level above the first voltage level, the function to represent an identification of a circuit including the memory array.
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公开(公告)号：US20190019545A1
公开(公告)日：2019-01-17
申请号：US16120107
申请日：2018-08-31
Applicant: Texas Instruments Incorporated
Inventor： Chiraag Juvekar , Joyce Kwong , Clive Bittlestone , Srinath Ramswamy
IPC: G11C11/22 , H04L9/32 , H01L27/11507
CPC classification number: G11C11/2295 , G11C11/221 , G11C11/2273 , G11C11/2275 , G11C11/2277 , H01L27/11507 , H04L9/3278
Abstract: Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.
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公开(公告)号：US10152613B2
公开(公告)日：2018-12-11
申请号：US15898935
申请日：2018-02-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Joyce Kwong , Clive Bittlestone , Manish Goel
Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.
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公开(公告)号：US20170353194A1
公开(公告)日：2017-12-07
申请号：US15686361
申请日：2017-08-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yaoyu Tao , Joyce Kwong
IPC: H03M13/11
CPC classification number: H03M13/1117 , H03M13/1108 , H03M13/1111 , H03M13/1142 , H03M13/116
Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.
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公开(公告)号：US20170149446A1
公开(公告)日：2017-05-25
申请号：US14950659
申请日：2015-11-24
Applicant: Texas Instruments Incorporated
Inventor： Yaoyu Tao , Joyce Kwong
IPC: H03M13/11
CPC classification number: H03M13/1117 , H03M13/1108 , H03M13/1111 , H03M13/1142 , H03M13/116
Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.
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