公开(公告)号：US20210211102A1

公开(公告)日：2021-07-08

申请号：US17210251

申请日：2021-03-23

Applicant: Texas Instruments Incorporated

Inventor： Vajeed Nimran ,  Raja Sekhar ,  Sandeep Oswal ,  Shagun Dusad

IPC: H03F1/56 ,  H03F3/45

Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.

公开(公告)号：US10583461B2

公开(公告)日：2020-03-10

申请号：US15852018

申请日：2017-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Miriyala ,  Naveen Kumar Ginige ,  Vajeed Nimran ,  Saugata Datta ,  Shabbir Amjhera Wala

IPC: B06B1/02 ,  H03K17/687 ,  A61B8/00

Abstract: A semiconductor device includes a trim storage and an encoder. The trim storage stores trim values. The encoder determines a magnitude of a supply voltage, determines a magnitude of a handle voltage, determines a source-to-handle voltage of a first transistor, and determines a source-to-handle voltage of a second transistor. Further, the encoder determines a target number of selectable first transistor units comprising the first transistor to select for the first transistor. Based on a trim value from the trim storage, the source-to-handle voltage of the first transistor and the source-to-handle voltage of the second transistor, the encoder determines a target number of selectable second transistor units comprising the second transistor to select for the second transistor. The encoder asserts control signals to select the target number of selectable first transistor units and the target number of selectable second transistor units.

公开(公告)号：US20180262169A1

公开(公告)日：2018-09-13

申请号：US15980771

申请日：2018-05-16

Applicant: Texas Instruments Incorporated

Inventor： Vajeed Nimran ,  Raja Sekhar ,  Sandeep Oswal ,  Shagun Dusad

IPC: H03F1/56 ,  H03F3/45 ,  H03G3/30 ,  H03G1/00

CPC classification number: H03F1/56 ,  G01S7/52033 ,  H03F3/45475 ,  H03F2203/45134 ,  H03F2203/45151 ,  H03F2203/45528 ,  H03F2203/45591 ,  H03G1/0035 ,  H03G3/3005 ,  H03G3/301

Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.