公开(公告)号：US11540384B2

公开(公告)日：2022-12-27

申请号：US17014143

申请日：2020-09-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shabbir Amjhera Wala ,  Xiaochen Xu ,  Dijeesh K ,  Abhishek Vishwa ,  Shriram Devi ,  Aatish Chandak ,  Sanjay Dixit ,  Elisa Maddalena Granata ,  Jun Shen ,  Sandeep Oswal

IPC: H05K1/00 ,  H05K1/02 ,  H04B1/40

Abstract: An apparatus comprises a transceiver (Tx/Rx) printed circuit board (PCB) with a top surface and a bottom surface and a power supply PCB. The Tx/Rx PCB includes two transmitter devices, each comprising a number N of channels. A first transmitter device is arranged on the bottom surface and a second transmitter device is arranged on the top surface over the first transmitter device. One or more pins of the second transmitter device are shorted with one or more pins of the first transmitter device with the same function. An analog front end (AFE) device comprising N input channels is arranged on the top surface of the Tx/Rx PCB, and a digital signal processor is coupled to the AFE device. The power supply PCB comprises a power supply module configured to provide a plurality of supply voltages to the Tx/Rx PCB and the power supply PCB.

公开(公告)号：US20250007580A1

公开(公告)日：2025-01-02

申请号：US18755227

申请日：2024-06-26

Applicant: Texas Instruments Incorporated

Inventor： Vajeed Nimran ,  Sachin Aithal ,  Shabbir Amjhera Wala ,  Rahul Reji

IPC: H04B7/06

Abstract: An example apparatus includes: at least one memory; programmable circuitry; and machine readable instructions to cause the programmable circuitry to at least: determine beamforming delay profiles for a plurality of channels, the beamforming delay profiles including delay values corresponding to a distance from a channel for a beamline; split the beamforming delay profiles into a plurality of segments; fit the plurality of segments of the beamforming delay profiles to linear segments; generate piece-wise beamforming delay profiles including initial values of the beamforming delay profiles, slopes of the linear segments of the plurality of segments, and durations of the plurality of segments; and store the piece-wise beamforming delay profiles for beamforming.

公开(公告)号：US20250004116A1

公开(公告)日：2025-01-02

申请号：US18755238

申请日：2024-06-26

Applicant: Texas Instruments Incorporated

Inventor： Vajeed Nimran ,  Sachin Aithal ,  Shabbir Amjhera Wala ,  Rahul Reji

IPC: G01S7/52 ,  G01S15/89 ,  H03M1/12

Abstract: An example apparatus includes: analog-to-digital converter (ADC) circuitry having an output terminal; beamforming circuitry including: delay circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the delay circuitry coupled to the output terminal of the ADC circuitry; amplifier circuitry having an input terminal and an output terminal, the input terminal of the amplifier circuitry coupled to the output terminal of the delay circuitry; and summation circuitry having an input terminal coupled to the output terminal of the amplifier circuitry; beamforming control circuitry coupled to the second input terminal of the delay circuitry, the beamforming control circuitry configured to calculate a delay value based on a piecewise delay profile.

公开(公告)号：US10583461B2

公开(公告)日：2020-03-10

申请号：US15852018

申请日：2017-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Miriyala ,  Naveen Kumar Ginige ,  Vajeed Nimran ,  Saugata Datta ,  Shabbir Amjhera Wala

IPC: B06B1/02 ,  H03K17/687 ,  A61B8/00

Abstract: A semiconductor device includes a trim storage and an encoder. The trim storage stores trim values. The encoder determines a magnitude of a supply voltage, determines a magnitude of a handle voltage, determines a source-to-handle voltage of a first transistor, and determines a source-to-handle voltage of a second transistor. Further, the encoder determines a target number of selectable first transistor units comprising the first transistor to select for the first transistor. Based on a trim value from the trim storage, the source-to-handle voltage of the first transistor and the source-to-handle voltage of the second transistor, the encoder determines a target number of selectable second transistor units comprising the second transistor to select for the second transistor. The encoder asserts control signals to select the target number of selectable first transistor units and the target number of selectable second transistor units.